LM5171 datasheet(40/89 Pages) TI2

40 / 89 page

DATA

REGADDR

DATA

REGADDR+n-1

DATA

REGADDR+n

7-bit target Address

8-bit Register Address

write

7-bit target Address

read

DATA

REGADDR+1

From controller to target

From target to controller

Start

Acknowlege

Stop

Not Acknowlege

Figure 7-5. Sequential READ Starting From A Defined Register Address

7.7 Single WRITE to a Defined Register Address

Figure 7-6 shows the format of a single write to a defined register address. First, the Controller issues a start

condition followed by a seven-bit I 2 C address. Next, the Controller writes a zero to signify that it wishes to

conduct a write operation. Upon receiving an acknowledge from the Peripheral, the Controller sends the eight-bit

to the defined value and the Controller writes the eight-bit data value. Upon receiving a third acknowledge the

device auto increments the I 2 C register address by one and the Controller issues a stop condition. This action

concludes the register write.

7-bit target Address

8-bit Register Address

DATA

REGADDR

write

From controller to target

From target to controller

Start

Acknowlege

Stop

Not Acknowlege

Figure 7-6. Single WRITE to Defined Register Address

7.8 Sequential WRITE Starting From A Defined Register Address

A sequential write operation is an extension of the single write protocol and shown in Figure 7-7 . If the Controller

does not send a stop condition after the device has issued an ACK, the device auto increments the register

address by one and the Controller writes to the next register.

7-bit target Address

8-bit Register Address

DATA

REGADDR

DATA

REGADDR+n-1

DATA

REGADDR+n

write

DATA

REGADDR+1

From controller to target

From target to controller

Start

Acknowlege

Stop

Not Acknowlege

Figure 7-7. Sequential WRITE Starting At A Defined Register Address

LM5171-Q1

SNVSC75B – APRIL 2023 – REVISED SEPTEMBER 2025

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