ADF4383 datasheet(34/80 Pages) AD

34 / 80 page

Data Sheet

ADF4383

APPLICATIONS INFORMATION

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Rev. 0 | 34 of 80

Figure 65. Single-Ended CMOS (RSER Is the Series Resistance.)

Figure 66. Differential, Low Voltage, Positive Emitter-Coupled Logic

(LVPECL)

Figure 67. Differential LVDS

Figure 68. Differential CML

Reference Phase Noise

The ADF4383 achieves an in-band normalized phase noise floor of

LNORM = −239 dBc/Hz in integer mode and LNORM= −237 dBc/Hz in

fractional mode.

To calculate the equivalent input phase noise floor (LIN) use the

following formula:

LIN=LNORM+10×log10fREF

(22)

For example, a 100 MHz reference input frequency gives an LIN of

−157 dBc/Hz in fractional mode. The phase noise of the reference

frequency source must be at least 6 dB less than LIN to avoid

impacting and increasing the overall system phase noise.

To maintain typical LNORM performance, Table 7 provides criteria

for selecting the optimal REF_SEL (Register 0x030, Bit 5) setting

based on the input reference signal type and amplitude.

SYNC INPUT NETWORK

The SYNC input pins may be programmed for CML/LVPECL or

LVDS interfaces using the SYNC_SEL bit to support a range of in-

put SYNC signal levels. Figure 69 to Figure 72 show recommended

input networks to SYNC input pins.

Figure 69. DC-Coupled Differential CML (Set SYNC_SEL = 0)

Figure 70. DC-Coupled Differential LVPECL (Set SYNC_SEL = 0)

Figure 71. DC-Coupled Differential LVDS (Set SYNC_SEL = 1)

Figure 72. DC-Coupled 3.3 V Single-Ended Logic to LVDS Input (Set

SYNC_SEL = 1)

OUTPUT PHASE NOISE CHARACTERISTICS

In-Band Output Phase Noise

Use the following equations to calculate the in-band phase noise

floor (LOUT) produced at fOUT:

ADF4383 Datasheet(PDF) 34 Page - Analog Devices