ADF4383 datasheet(21/80 Pages) AD

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Data Sheet

ADF4383

THEORY OF OPERATION

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Rev. 0 | 21 of 80

Table 9. BST_REF Programming

BST_REF

Sine Wave fREF (Vref)

≥1.4 V p-p

<1.4 V p-p

Reference Peak Detector

A reference input peak detection circuit is provided on the REFP

and REFN inputs to detect the presence of a reference signal and

provides the REF_OK status flag available through Bit 3, Register

0x058. The circuit has hysteresis to prevent the REF_OK flag from

chattering at the detection threshold.

The peak detector approximates an RMS detector; therefore, sine

and square wave inputs give different detection thresholds by a

factor of 4/π. See Table 10 for REF_OK detection values.

Table 10. REF_OK Status Output vs. Reference Input

REF_OK

Sine Wave fREF (mV p-p)

Square Wave fREF (mV p-p)

≥200

≥155

<180

<140

Reference Divider (R) and Doubler (D)

When the EN_RDBLR bit (Register 0x020, Bit 6) is set to 1, a

frequency multiplier is used to double the frequency driven to the

reference divider. A 6-bit divider, R_DIV (Register 0x020, Bits[5:0]),

in series with reference doubler is used to reduce the frequency

seen at the PFD. Its divide ratio, R, can be set to any integer from

1 to 63, inclusive. Use the R_DIV bits to directly program the R-di-

vide ratio. See the Output Frequency section for the relationship

between R and D and the fREF, fPFD, fVCO, and fRFOUT frequencies.

When using the reference doubler, refer to Table 11 for the required

bit field settings that must be used for optimal jitter performance.

Target reference frequency refers to the reference frequency after

the doubler stage.

Table 11. Reference Doubler Settings

Target

Reference

Frequency

RDBLR_DEL_SEL

RDBLR_DC

INV_RDBLR

<1 GHz

≤1.6 GHz

1.6 GHz to

4.5 GHz

Phase/Frequency Detector (PFD)

The PFD, in conjunction with the charge pump, produces source

and sink current pulses proportional to the phase difference be-

tween the outputs of the reference divider or reference doubler and

feedback divider. These source and sink pulses are required to

phase lock the loop, forcing a phase alignment at the inputs of the

PFD. See Figure 47 for a simplified schematic of the PFD.

Figure 47. Simplified PFD Schematic

Charge Pump

The charge pump, controlled by the PFD, forces sink (down) or

source (up) current pulses onto the CP pin, which must be connect-

ed to an appropriate loop filter. See Figure 48 for a simplified

schematic of the charge pump.

Figure 48. Simplified Charge Pump Schematic

The output current magnitude ICP can be set from 0.79 mA to 11.1

mA using the CP_I bits (Register 0x001F, Bits[3:0]). A larger ICP

can result in lower in-band noise due to the lower impedance of

the loop filter components, while a smaller ICP can result in better

spurious performance. See Table 12 for charge pump programming

values.

Table 12. CP Programming

CP_I, Bits[3:0]

ICP (mA)

0.79

0.99

1.19

1.38

1.59

1.98

2.39

2.79

3.18

3.97

4.77

5.57

6.33

7.91

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