ADF4383 datasheet(24/80 Pages) AD

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Data Sheet

ADF4383

THEORY OF OPERATION

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Rev. 0 | 24 of 80

Lock Detector

The lock detector uses internal signals from the PFD to measure

the phase difference between the output signal of the reference

divider and doubler (RCLK) and the output signal of the feedback

divider (NCLK) in Figure 47. This detector is enabled by setting

both the EN_LOL and EN_LDWIN bits (Register 0x02D, Bit 5 and

Bit 4, respectively) to 1 and presents the lock detector output on

the LKDET pin (Pin 27) and the LOCKED bit (Register 0x58, Bit 0).

The lock detector output can also be presented on the MUXOUT

pin (Pin 37 by programming the MUXOUT bits in Register 0x2E,

Bits[7:4], to b0001).

The PFD RCLK and NCLK phase difference must be less than the

phase difference lock window time, tLDWIN, for a set number of PFD

cycles before the lock detector output indicates the PLL has locked.

The desired number of PFD cycles vary depending on whether the

lock detect accuracy or speed is prioritized. Five loop filter time

constants can be used as an initial estimate of the desired number

of PFD cycles, as shown in the following equation:

PFD

Cycles= 52×π×LFBW×fPFD

(11)

where LFBW means loop filter bandwidth.

Note that LD_COUNT bits (Register 0x02C, Bits[4:0]) are used to

select the desired number of PFD cycles. Use Table 15 to select the

LD_COUNT value for the desired number of PFD cycles.

Table 15. LD_COUNT Programming

LD_COUNT[4:0]

PFD Cycles

131

195

259

387

515

771

1027

1539

2051

3075

4099

6147

8195

12291

16387

24579

32771

49155

Table 15. LD_COUNT Programming (Continued)

LD_COUNT[4:0]

PFD Cycles

65539

98307

131075

196611

262147

393219

524291

786345

1048579

Figure 50. Lock Detector Timing, Bleed Current Disabled

Table 16. Lock Detector Timing, Bleed Current Disabled

Region

Absolute Phase

Difference at PFD

Lock Detector State

>tLDWIN

Low

<tLDWIN

Low, counts PFD cycles

High, greater than or equal to the desired

PFD cycle count

<tLDWIN

High

>tLDWIN

Low (immediately)

When the charge pump bleed current is enabled, a phase offset is

applied to the PFD inputs. This phase offset, tIDEL, is proportional to

the amount of bleed current. Region 3 and Region 4 in Figure 50

and Figure 51 highlight the PFD phase difference the PLL settles

to when the charge pump bleed current is disabled or enabled,

respectively.

Figure 51. Lock Detector Timing, Bleed Current Enabled

For proper operation of the lock detector, the absolute value of tIDEL

must be less than tLDWIN. The user sets the phase difference lock

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