DM505 datasheet(146/295 Pages) TI2

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I2Ci_SDA

I2Ci_SCL

SPRS91v_I2C_02

146

DM505

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Specifications

(1) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.

(2) Software must properly configure the I2C module registers to achieve the timings shown in this table. See the Device TRM for details.

Figure 5-39. I2C Transmit Timing

5.9.6.9

UART

The UART performs serial-to-parallel conversions on data received from a peripheral device and parallel-

to-serial conversion on data received from the CPU. There are 3 UART modules in the device. Each

UART can be used for configuration and data exchange with a number of external peripheral devices or

interprocessor communication between devices.

The UARTi (where i = 1 to 3) include the following features:

•

16C750 compatibility

•

64-byte FIFO buffer for receiver and 64-byte FIFO for transmitter

•

Baud generation based on programmable divisors N (where N = 1…16 384) operating from a fixed

functional clock of 48 MHz or 192 MHz

•

Break character detection and generation

•

Configurable data format:

–

Data bit: 5, 6, 7, or 8 bits

–

Parity bit: Even, odd, none

–

Stop-bit: 1, 1.5, 2 bit(s)

•

Flow control: Hardware (RTS/CTS) or software (XON/XOFF)

NOTE

For more information, see the UART section of the Device TRM.

Table 5-43, Table 5-44 and Figure 5-40 assume testing over the recommended operating conditions and

electrical characteristic conditions below.

Table 5-43. Timing Requirements for UART

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

tw(RX)

Pulse width, receive data bit, 15/30/100pF high or low

0.96U(1)

1.05U(1)

tw(CTS)

Pulse width, receive start bit, 15/30/100pF high or low

0.96U(1)

1.05U(1)

td(RTS-TX)

Delay time, transmit start bit to transmit data

P(2)

td(CTS-TX)

Delay time, receive start bit to transmit data

P(2)

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