DM505 datasheet(149/295 Pages) TI2

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DM505

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SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Specifications

Table 5-46. Timing Requirements for SPI - Master Mode (continued)

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

SM8

td(CS-SPICLK)

Delay time, spi_cs[x] active to spi_sclk first edge (1)

MASTER

_PHA0

(4)

B-4.2 (5)

MASTER

_PHA1

(4)

A-4.2 (6)

SM9

td(SPICLK-CS)

Delay time, spi_sclk last edge to spi_cs[x] inactive (1)

MASTER

_PHA0

(4)

A-4.2 (6)

MASTER

_PHA1

(4)

B-4.2 (5)

(1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture

input data.

(2) Related to the SPI_CLK maximum frequency.

(3) P = SPICLK period.

(4) SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.

(5) B = (TCS + 0.5) × TSPICLKREF × Fratio, where TCS is a bit field of the SPI_CH(i)CONF register and Fratio = Even

≥2.

(6) When P = 20.8 ns, A = (TCS + 1) × TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register. When P > 20.8 ns, A = (TCS

+ 0.5) × Fratio × TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register.

(7) The IO timings provided in this section are applicable for all combinations of signals for spi1 and spi2. However, the timings are only

valid for spi3 and spi4 if signals within a single IOSET are used. The IOSETs are defined in the following tables.

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