DM505 datasheet(148/295 Pages) TI2

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DM505

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Specifications

Table 5-45. UART1-3 IOSETs (continued)

SIGNALS

IOSET1

IOSET2

IOSET3

BALL

MUX

BALL

MUX

BALL

MUX

uart3_ctsn

5.9.6.10 McSPI

The McSPI is a master/slave synchronous serial bus. There are four separate McSPI modules (SPI1,

SPI2, SPI3, and SPI4) in the device. All these four modules support up to four external devices (four chip

selects) and are able to work as both master and slave.

The McSPI modules include the following main features:

•

Serial clock with programmable frequency, polarity, and phase for each channel

•

Wide selection of SPI word lengths, ranging from 4 to 32 bits

•

Up to four master channels, or single channel in slave mode

•

Master multichannel mode:

–

Full duplex/half duplex

–

Transmit-only/receive-only/transmit-and-receive modes

–

Flexible input/output (I/O) port controls per channel

–

Programmable clock granularity

–

SPI configuration per channel. This means, clock definition, polarity enabling and word width

•

Power management through wake-up capabilities

•

Programmable timing control between chip select and external clock generation

•

Built-in FIFO available for a single channel.

•

Each SPI module supports multiple chip select pins spim_cs[i], where i = 1 to 4.

NOTE

For more information, see the Serial Communication Interface section of the device TRM.

NOTE

The McSPIm module (m = 1 to 4) is also referred to as SPIm.

Table 5-46, Figure 5-41 and Figure 5-42 present Timing Requirements for McSPI - Master Mode.

Table 5-46. Timing Requirements for SPI - Master Mode

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

SM1

tc(SPICLK)

Cycle time, spi_sclk (1) (2)

SPI1/2/3/

20.8

SM2

tw(SPICLKL)

Typical Pulse duration, spi_sclk low (1)

0.5×P-1

(3)

SM3

tw(SPICLKH)

Typical Pulse duration, spi_sclk high (1)

0.5×P-1

(3)

SM4

tsu(MISO-SPICLK)

Setup time, spi_d[x] valid before spi_sclk active edge (1)

2.29

SM5

th(SPICLK-MISO)

Hold time, spi_d[x] valid after spi_sclk active edge (1)

2.67

SM6

td(SPICLK-SIMO)

Delay time, spi_sclk active edge to spi_d[x] transition (1)

SPI1/2/4

-3.57

3.57

SPI3

-3.57

3.57

SM7

td(CS-SIMO)

Delay time, spi_cs[x] active edge to spi_d[x] transition

3.57

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