TDA2SA datasheet(368/427 Pages) TI2

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368

TDA2SX, TDA2SG, TDA2SA

TDA2HG, TDA2HV, TDA2HF, TDA2LF

SPRS951F – DECEMBER 2015 – REVISED MAY 2019

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Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF

Applications, Implementation, and Layout

8.5.2.3.4 ESD Protection System Design Consideration

ESD protection system design consideration is covered in Section 8.5.2.2 of this document. The following

are additional considerations for ESD protection in a system.

•

Metallic shielding for both ESD and EMI

•

Chassis GND isolation from the board GND

•

Air gap designed on board to absorb ESD energy

•

Clamping diodes to absorb ESD energy

•

Capacitors to divert ESD energy

•

The use of external ESD components on the DP/DM lines may affect signal quality and are not

recommended.

8.5.2.4

References

•

USB 2.0 Specification, Intel, 2000, http://www.usb.org/developers/docs/

•

High

Speed

USB

Platform

Design

Guidelines,

Intel,

2000,

http://www.intel.com/technology/usb/download/usb2dg_R1_0.pdf

•

Selection and Specification of Crystals for Texas Instruments USB 2.0 Devices (SLLA122)

8.5.3

USB 3.0 Board Design and Layout Guidelines

This section provides the timing specification for the USB3.0 (USB1 in the device) interface as a PCB

design and manufacturing specification. The design rules constrain PCB trace length, PCB trace skew,

signal integrity, cross-talk, and signal timing. TI has performed the simulation and system design work to

ensure the USB3.0 interface requirements are met. The design rules stated within this document are

targeted at DEVICE mode electrical compliance. HOST mode and/or systems that do not include the 3m

USB cable and far-end 11-inch PCB trace required by DEVICE mode compliance testing may not need

the complete list of optimizations shown in this document; however, applying these optimizations to HOST

mode systems will lead to optimal DEVICE mode performance.

8.5.3.1

USB 3.0 interface introduction

The USB 3.0 has two unidirectional differential pairs: TXp/TXn pair and RXp/RXn pair. AC coupling caps

are needed on the board for TX traces.

Figure 8-39 present high level schematic diagram for USB 3.0 interface.

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