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TDA2SA Datasheet(PDF) 370 Page - Texas Instruments |
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TDA2SA Datasheet(HTML) 370 Page - Texas Instruments |
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370 / 427 page  370 TDA2SX, TDA2SG, TDA2SA TDA2HG, TDA2HV, TDA2HF, TDA2LF SPRS951F – DECEMBER 2015 – REVISED MAY 2019 www.ti.com Submit Documentation Feedback Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF Applications, Implementation, and Layout Copyright © 2015–2019, Texas Instruments Incorporated 8.5.3.2 USB 3.0 General routing rules Some general routing guidelines regarding USB 3.0: • Avoid crossing splits reference plane(s). • Shorter trace length is preferred. • Minimize the via usage and layer transition • Keep large spacing between TX and RX pairs. • Intra-lane delay mismatch between DP and DM less than 1ps. Same for RXp and RXn. • Distance between common mode filter (CMF) and ESD protection device should be as short as possible • Distance between ESD protection device and USB connector should be as short as possible. • Distance between AC capacitors (TX only) and CMF should be as short as possible. • USB 3.0 signals should always be routed over an adjacent ground plane. Table 8-13 and Table 8-14 present routing specification and recommendations for USB1 in the device. Table 8-13. USB1 Routing Specifications PARAMETER MIN TYP MAX UNIT Device balls to USB 3.0 connector trace length 3500 Mils Skew within a differential pair 3 6 Mils Number of stubs allowed on TX/RX traces 0 Stubs TX/RX pair differential impedance 83.7 90 96.3 Ω Number of vias on each TX/RX trace (1) 2 Vias Differential pair to any other trace spacing (2) (3) (4) 2xDS 3xDS Number of ground plane cuts allowed within USB3 routing region (except for specific ground carving as explained in this document) 0 Cuts Number of layers between USB3.0 routing region and reference ground plane 0 Layers PCB trace width 6 Mils PCB BGA escape via pad size 18 Mils PCB BGA escape via hole size 10 Mils (1) Vias must be used in pairs and spaced equally along a signal path. (2) DS = differential spacing of the traces. (3) Exceptions may be necessary in the SoC package BGA area. (4) GND guard-bands on the same layer may be closer, but should not be allowed to affect the impedance of the differential pair routing. GND guard-bands to isolate USB3.0 differential pairs from all other signals are recommended. Table 8-14. USB1 Routing Recommendations Item Description Reason ESD location Place ESD component on same layer as connector (no via or stub to ESD component) Eliminate reflection loss from via & stub to ESD ESD part number TPD1E05U06 Minimize capacitance (0.42pF) CMF part number DLW21SN900HQ2 Manufacturer’s recommended device Connector Use USB3.0 connector with supporting s-parameter model Enable full signal chain simulation Carve Ground Carve GND underneath AC Caps, ESD, CMF, and connector Minimize capacitance under ESD and CMF Round pads Minimize pad size and round the corners of the pads for the ESD and CMF components Minimize capacitance |
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