TDA2SA datasheet(371/427 Pages) TI2

371 / 427 page

Layer2, GND: Gaps carved in GND underneath

AC Caps, CMF, ESD, and connector.

Layer3, Signal: Implement as keep-out

zone underneath carved GND areas.

Layer4, GND Plane underneath AC Caps,

CMF, ESD, and connector.

SPRS85x_PCB_USB30_3

Top Layer: Routing from SoC through

AC Caps, CMF, and ESD to connector.

AC Cap

CMF

AC Cap

371

TDA2SX, TDA2SG, TDA2SA

TDA2HG, TDA2HV, TDA2HF, TDA2LF

www.ti.com

SPRS951F – DECEMBER 2015 – REVISED MAY 2019

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Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF

Applications, Implementation, and Layout

Table 8-14. USB1 Routing Recommendations (continued)

Item

Description

Reason

Vias

Max 2 vias per signal trace. If vias are required, place vias close to

the AC Caps and CMFs. Vias under the SoC grid array may be used

if necessary to route signals away from BGA pattern.

Vias significantly degrade signal

integrity at 2.5GHz

Figure 8-41 presents an example layout, demonstrating the “carve GND” concept.

Figure 8-41. USB 3.0 Example “carve GND” layout

8.5.4

HDMI Board Design and Layout Guidelines

This section provides the timing specification for the HDMI interface as a PCB design and manufacturing

specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,

and signal timing. TI has performed the simulation and system design work to ensure the HDMI interface

requirements are met. The design rules stated within this document are targeted at resolutions less than

or equal to 1080p60 with 8-bit color; deep color (10-bit) requires further signal integrity optimization.

8.5.4.1

HDMI Interface Schematic

The HDMI bus is separated into three main sections (HDMI Ethernet and the optional Audio Return

Channel are not specifically supported by this Device):

1. Transition Minimized Differential Signaling (TMDS) high speed digital video interface

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