MP5611

– 2.9V TO 5.2V INPUT, TRIPLE-OUTPUT, AMOLED POWER SUPPLY

MP5611 Rev. 1.0

MonolithicPower.com

12

12/16/2021

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OPERATION

The

MP5611

is

a

triple-output

converter

designed for small-size AMOLED (active matrix

organic

light-emitting diode)

display power

supplies. It integrates a boost converter for

ELVDD, an inverting buck-boost (IBB) converter

for ELVSS, and another boost converter for

AVDD. The one wire digital control pin (CTRL)

can program the ELVSS, ELVDD, and AVDD

voltages following digital protocol.

Feedback (FB) Connection for ELVDD

If the FB pin is floating or tied to GND, or (VELVDD

- VFB) > 350mV, then the ELVDD boost

converter

’s output voltage (VOUT) is sensed via

the ELVDD pin directly. To improve the ELVDD

VOUT sense performance, externally connect FB

to the main

ELVDD output capacitor’s positive

terminal. In this case, when (VELVDD - VFB) <

250mV, VOUT is sensed via FB pin with better

sense accuracy.

Fast Discharge Function

Pull the FD pin high to enable the active fast

discharge function when the MP5611 shuts

down. By connecting FD to GND, all outputs are

high-impedance when the IC shuts down. When

FD is pulled high, the fast discharge function can

also be disabled by applying 81 pulses to the

CTRL pin.

Figure 3 shows the start-up/shutdown sequence,

where the solid line is with active discharge

enabled and the dotted line is without active

discharge enabled.

VIN

EN_AVDD

AVDD

CTRL

ELVDD

ELVSS

~1.5ms

5.8V

~0.5ms

4.6V

-4V

~0.5ms

10ms

10ms

UVLO

UVLO

Figure 3: Start-Up/Shutdown Sequence with and without Active Discharge Enable

Configuring the ELVSS Transition Time

When ELVSS is controlled by the CTRL pulse,

the voltage transition time can be configured by

the capacitor on the CT pin (CEXTERNAL), which

can be estimated using Equation (1):

t (µs) = 3 x RINTERNAL (kΩ) x CEXTERNAL (nF) (1)

Where RINTERNAL = 300kΩ. CEXTERNAL e.g. 100nF

is about 90ms of the transition time.

Digital Interface (CTRL)

The CTRL pin has two functions:

1. CTRL is the digital interface that configures

the output of ELVSS, ELVDD, and AVDD, as

well as the output over-current (OC) limit.

The number of pulse signal

’s rising edges

applied on the CTRL pin is counted for

configuring the corresponding item to a

certain value (see Table 1 on page 13).

2. CTRL is also ELVDD and ELVSS

’s enable

signal. Once CTRL pulls high, ELVDD starts

up to the default value. After 10ms, ELVSS

establishes to its default value (see the

Timing Diagram section on page 6).

The reset information for ELVSS, ELVDD, and

AVDD follows:

• A power cycle resets all settings to default.

• CTRL is low, and lasts for a set time to reset

ELVDD and ELVSS to the default value.

• EN_AVDD can enable/disable AVDD.

• EN_AVDD and CTRL are both pulled low to

reset AVDD and all registers to the default

value.