DA9233 datasheet(28/50 Pages) RENESAS

28 / 50 page

DA9233

Integrated Ultra-Low Quiescent Current, Ultra-Low

Output Ripple Buck Regulator with 100 mA LDO

Datasheet

Revision 2.2

13-Jun-2023

CFR0011-120-00 Rev 5

28 of 50

10.6 I2C Programming

10.6.1

Interface Description

DA9233 includes an I2C compatible interface based on the following signals:

● SCL: standard 400 kHz I2C bus serial clock generated by the Host processor

● SDA: standard 400 kHz I2C bus serial address/data input output

SDA and SCL are open drain I/O terminals. The standard frequency of the I2C bus is 400 kHz in fast

mode or 100 kHz in slow mode.

SCL

SDA

Serial Interface

I2C

Figure 189: I2C Serial Interface Pins

The I2C bus is used to control most functions and change register values depending on the

application requirements. In active battery, the I2C circuitry is powered from the battery. The interface

maintains a proper operation as long as VDD_SYS is valid.

The device is compatible with the standard I2C protocol but only operates as a slave. The transfer

protocol is the same whether operating in fast or slow mode.

10.6.2

Details of the I2C Protocol

The device supports 7-bit addressing only, the address is 0x2F. The 8-bit shifted address is 0x5E.

A timer runs during I2C transitions. If the timer expires while SDA is held low, all additional

commands are ignored and the I2C state machine is reset. The timer is reset with a START condition

and stopped with a STOP condition.

The I2C bus is monitored at all times for a valid SLAVE address, and an acknowledge bit is

generated if the SLAVE address was true.

● A START condition is initiated by a high to low transition on the SDA line while the SCL is in the

high state.

● A STOP condition is indicated by a low to high transition on the SDA line while the SCL is in the

high state.

● An ACKNOWLEDGE is indicated by the receiver pulling the SDA line low during the following

clock cycle.

SDA

SCL

Data SDA must be stable

during high part of clock

SCL

Data sampled on SCL

rising edge and driven on

SCL falling edge

Start ( S ) is SDA falling while

SCL high

Stop (P ) is SDA rising while

SCL high

Figure 20: I2C Start and Stop Conditions

DA9233 Datasheet(PDF) 28 Page - Renesas Technology Corp

DA9233 Datasheet(HTML) 28 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Datasheet Download

Link URL