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AFE7950 Datasheet(PDF) 28 Page - Texas Instruments |
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AFE7950 Datasheet(HTML) 28 Page - Texas Instruments |
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28 / 126 page ![]() 4.11 Switching Characteristics Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; TX Input Rate = 491.52MSPS, fDAC = 8847.36MSPS; fADC = 2949.12MSPS; nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation =0dB; SerDes rate = 24.33Gbps; unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TX Channel Latency tJESDTX JESD to TX output Latency LMFSHd=2-8-8-1, 368.64 MSPS input rate, 24x Interpolation, Serdes rate = 16.22Gbps (JESD204C) 152 interface clock cycles(1) LMFSHd=8-16-4-1, 491.52 MSPS 24x Interpolation, Serdes rate = 16.22Gbps (JESD204C) 176 LMFSHd=4-16-8-1, 245.76 MSPS 48x Interpolation, Serdes rate = 16.22Gbps (JESD204C) 124 LMFSHd=2-16-16-1, 122.88 MSPS 96x Interpolation, Serdes rate = 16.22Gbps (JESD204C) 97 RX Channel Latency SerDes Transmitter Analog Delay 3.6 ns tJESDRX RX input to JESD output Latency LMFS=2-16-16-1, 122.88 MSPS, 24x Decimation, Serdes rate = 16.22Gbps (JESD204C) 92 interface clock cycles(1) LMFS=4-16-8-1, 245.76 MSPS, 12x Decimation, Serdes rate = 16.22Gbps (JESD204C) 108 LMFS=4-8-4-1, 491.52 MSPS, 6x Decimation, Serdes rate = 16.22Gbps (JESD204C) 153 FB Channel Latency SerDes Transmitter Analog Delay 3.6 ns tJESDFB FB input to JESD output Latency LMFS=1-2-8-1, 368.64 MSPS, 8x Decimation 151 interface clock cycles(1) LMFS=2-4-4-1, 491.52 MSPS, 6x Decimation 177 (1) Interface clock cycles is the period of the digital interface sample rate, e.g. 1GSPS = 1ns. AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 www.ti.com 28 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: AFE7950-SP |
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