 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AFE7950 Datasheet(PDF) 59 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
AFE7950 Datasheet(HTML) 59 Page - Texas Instruments |
|
|
59 / 126 page  4.12.5 TX Typical Characteristics at 4.9GHz (continued) Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC = 11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1dBFS, DSA = 0dB, Sin(x)/x enabled, DSA calibrated DSA (dB) 0 4 8 12 16 20 24 28 32 36 40 -0.1 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 1TX 2TX 3TX 4TX fDAC = 11796.48MSPS, interleave mode, matching at 4.9GHz Integrated Gain Error = POUT(DSA Setting) – POUT(DSA Setting = 0) + (DSA Setting) Figure 4-155. TX Calibrated Integrated Gain Error vs DSA Setting and Channel at 4.9GHz DSA (dB) 0 4 8 12 16 20 24 28 32 36 40 -0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 0.05 -40 qC 25 qC 105 qC fDAC = 11796.48MSPS, interleaved mode, matching at 4.9GHz Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1 Figure 4-156. TX Uncalibrated Differential Gain Error vs DSA Setting and Temperature at 4.9GHz DSA (dB) 0 4 8 12 16 20 24 28 32 36 40 -0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 -40 qC 25 qC 105 qC fDAC = 11796.48MSPS, interleaved mode, matching at 4.9GHz Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1 Figure 4-157. TX Calibrated Differential Gain Error vs DSA Setting and Temperature at 4.9GHz DSA (dB) 0 4 8 12 16 20 24 28 32 36 40 -0.05 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 -40 qC 25 qC 105 qC fDAC = 11796.48MSPS, interleaved mode, matching at 4.9GHz Integrated Gain Error = POUT(DSA Setting) – POUT(DSA Setting = 0) + (DSA Setting) Figure 4-158. TX Uncalibrated Integrated Gain Error vs DSA Setting and Temperature at 4.9GHz DSA (dB) 0 4 8 12 16 20 24 28 32 36 40 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 -40 qC 25 qC 105 qC fDAC = 11796.48MSPS, interleaved mode, matching at 4.9GHz Integrated Gain Error = POUT(DSA Setting) – POUT(DSA Setting = 0) + (DSA Setting) Figure 4-159. TX Calibrated Integrated Gain Error vs DSA Setting and Temperature at 4.9GHz DSA (dB) 0 4 8 12 16 20 24 28 32 36 40 -0.1 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 1TX 2TX 3TX 4TX fDAC = 11796.48MSPS, interleaved mode, matching at 4.9GHz Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting) Figure 4-160. TX Uncalibrated Differential Phase Error vs DSA Setting and Channel at 4.9GHz www.ti.com AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 59 Product Folder Links: AFE7950-SP |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
