AD4693 datasheet(49/77 Pages) AD

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Data Sheet

AD4693/AD4694

APPLICATIONS INFORMATION

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Rev. 0 | 49 of 77

PRIORITY SEQUENCE SCHEME

The priority sequence scheme is a method for programming the

advanced sequencer to achieve a set of high priority channels

(higher sampling rates and higher averaging ratios) and low priority

channels (lower sampling rates and lower averaging ratios). The

following describes how to implement a priority sequencing scheme

using the AD4693/AD4694 advanced sequencer mode.

Figure 87 shows a generalized channel sequence with two priority

levels. Channels are grouped into high priority (HP) and low priority

(LP) channels. The LP channels are sampled once per sequence,

while the HP channels are sampled multiple times per sequence.

Alternatively, the channel sequence can be thought of as a group-

ing of subsequences, where all of the HP channels are sampled

once per subsequence, but only one LP channel is sampled per

subsequence.

Figure 87. Sequence of HP and LP Channels in Two-Priority Channel

Sequence

The number of LP and HP channels dictate the length of the entire

channel sequence and their effective sample rates. The number

of advanced sequencer slots needed to implement the two priority

sequence scheme (NSLOTS) is defined by the following equation:

NSLOTS=NLP× NHP + 1

(6)

where:

NLP is the number of LP channels.

NHP is the number of HP channels.

The maximum value of NSLOTS needed to implement a two priority

sequence scheme is when NLP = NHP = 8 channels, where NSLOTS

= 72 slots.

Because the LP channels are only sampled once per NSLOTS

channels, their effective sampling frequency (fS_LP) is as follows:

fS_LP= fSNSLOTS

(7)

Because the HP channels are sampled once for each LP channel,

their effective sampling frequency (fH_LP) is as follows:

fS_HP=fS× NLPNSLOTS

(8)

Table 23 and Figure 88 show an example two-priority sequence

with IN0, IN1, and IN2 as HP channels and IN3 and IN4 as LP

channels. NSLOTS is 8 in this example, so the NUM_SLOTS_AS

bit field is set to 0x7. The sequence slot channel assignments are

set via the AS_SLOTx registers, as described in the Advanced

Sequencer Mode section. In this example, configuring the HP

channels accumulator depths to twice the LP channels accumulator

depths ensures all channels have the same output data rate. Figure

88 shows an example where the HP channels depth is 4 and the LP

channels depth is 2, and each channel therefore has an output data

rate of fS/16.

Table 23. Two-Priority Example with Sampling Rates and Output Data Rates

Slot Number

Slot Channel

Channel Effective Sampling

Rate

Accumulator Depth (i.e.

Averaging Ratio)

Output Data Rate

IN0

fS/4

fS/16

IN1

fS/4

fS/16

IN2

fS/4

fS/16

IN3

fS/8

fS/16

IN0

fS/4

fS/16

IN1

fS/4

fS/16

IN2

fS/4

fS/16

IN4

fS/8

fS/16

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