AD4693 datasheet(29/77 Pages) AD

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Data Sheet

AD4693/AD4694

THEORY OF OPERATION

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Rev. 0 | 29 of 77

Standard Sequencer Mode

Standard sequencer mode is the simpler of the two sequencer

modes and is recommended when every channel needs the same

output data rate and when arbitrary channel orders are not re-

quired.

In standard sequencer mode, the channel sequencer scans through

a preprogrammed set of enabled channels in ascending order.

Each channel is enabled or disabled through their corresponding

INx_EN bits in the STD_SEQ_CONFIG register. The sequencer

scans through each enabled channel in ascending order and skips

each disabled channel. Each enabled channel is therefore sampled

once per sequence iteration. Figure 56 and Figure 57 show exam-

ples where the standard sequencer and four analog inputs (IN0,

IN2, IN5, and IN7) are enabled in the sequence.

Standard sequencer mode is selected by setting the SEQ_MODE

bit to 1 in the SEQ_CTRL register. The INx_EN bits in the

STD_SEQ_CONFIG register configure each INx channel as ena-

bled (INx_EN = 1) or disabled (INx_EN = 0). The STD_SEQ_CON-

FIG register is a 16-bit wide register and must be written to in its

entirety in one SPI frame (see the Register Length section). By

default, the channel sequencer is in standard sequencer mode with

IN0 enabled and all other channels disabled.

A state reset is required to update the internal state of the channel

sequencer after updating the SEQ_MODE bit or the INx_EN bits

(see the State Reset section). In standard sequencer mode, the

multiplexer channel is set to the lowest-numbered enabled channel

in the sequence following a state reset.

Figure 56. Standard Sequencer Simplified Diagram

Figure 57. Standard Sequencer Example Timing Diagram

AD4693 Datasheet(PDF) 29 Page - Analog Devices