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SL811S/T
Document #: 38-08009 Rev. **
Page 25 of 27
7.5.4
SL811S DMA Read Cycle
Note:
12. Data is held until nDACK goes high regardless of state of nREAD.
Parameter
Description
Min.
Typ.
Max.
tdack
nDACK low
100 ns
tddrdlo
nDACK to nRD low delay
0 ns
tdckdr
nDACK low to nDRQ high delay
5 ns
tdrdp
nRD pulse width
90 ns
tdhld[12]
Date hold after nDACK high
5 ns
tddaccs
Data access from nDACK low
85 ns
tdrdack
nRD high to nDACK high
0 ns
tdakrq
nDRQ low after nDACK high
5 ns
trdcycle
DMA Read Cycle Time
150 ns
n DRQ
n D A CK
D0 -D 7
DA T A
n RD
S L 8 11 DM A RE AD CY C L E T IM ING
tdrd p
td accs
td ack
tdhld
tdd rdlo
tdckdr
tda krq