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LXT362 Datasheet(PDF) 7 Page - Intel Corporation |
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LXT362 Datasheet(HTML) 7 Page - Intel Corporation |
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7 / 48 page  Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT362 Datasheet 7 Figure 1. LXT362 Block Diagram INTERNAL PATTERN GENERATOR (QRSS) TCLK RCLK MCLK TPOS RPOS TNEG RNEG MODE TRSTE QRSS ENABLE NLOOP ENABLE DECODER ENABLE QPD ENABLE RLOOP ENABLE LLOOP ENABLE ALOOP ENABLE AIS ENABLE/ REPORT TAOS ENABLE CONTROL MONITOR EC Select ENCODER ENABLE B8ZS/HDB3 UNIPOLAR ENCODER ANALOG LOOPBACK TRANSMIT TIMING CONTROL LINE DRIVERS TRANSMIT ATTENUATION & FILTER EC1/ EGL 4 EC4-1 TTIP TRING CLKE INT SCLK SDI SDO RRING RTIP JASEL NLOOP LOS/ QPD QPD INTERNAL PATTERN DETECTOR INBAND NLOOP DETECTOR LOS B8ZS/HDB3 UNIPOLAR DECODER CLOCK GENERATOR TIMING & DATA RECOVERY EQUALIZER CONTROL NOISE & CROSSTALK FILTER SLICERS & PEAK DETECTORS GAIN RECEIVE EQUALIZER AIS DETECTOR LOS PROCESSOR JA IF SELECTED JA IF SELECTED LOCAL LOOPBACK REMOTE LOOPBACK JITTER ATTENUATOR CS SERIAL PORT CONTROL/STATUS REGISTERS |
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