Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT362

Datasheet

29

3.0

Register Definitions

The LXT362 contains five read/write and three read-only registers that are accessible in Host mode

via the serial I/O port. Table 7 lists the LXT362 register addresses. Only bits A6 through A1 of the

address byte are valid (the address decoder ignores bits A7 and A0) while A0 functions as the read/

write (R/W) bit. Table 8 identifies the name of each register bit. Table 9 through Table 17 describe

the function of the bits in each register.

Note that upon power-up or reset, all registers are cleared to 0.

Table 7.

Register Addresses

Register

A7 - A1

Name

Abbr

Control #1

CR1

x010000

Control #2

CR2

x010001

Control #3

CR3

x010010

Interrupt Clear

ICR

x010011

Transition Status

TSR

x010100

Performance Status

PSR

x010101

Equalizer Status

ESR

x010110

Control #4

CR4

x010111

1. x = don’t care

2. Address A0 is the read/write (R/W) bit.

Table 8.

Register and Bit Summary

Register

Bit

Name

Type

7

6

5

4

32

10

Control #1

CR1

R/W

JASEL1

JASEL0

ENCENB

UNIENB

EC4

EC3

EC2

EC1

Control #2

CR2

R/W

RESET

EPAT1

EPAT0

ETAOS

ENLOOP

EALOOP

ELLOOP

ERLOOP

Control #3

CR3

R/W

JA6HZ

SBIST

EQZMON

ES64

ESCEN

ESJAM

Interrupt Clear

ICR

R/W

CESU

CESO

CDFMO

CQRSS

CAIS

CNLOOP

CLOS

Transition

Status

TSR

R

ESUNF

ESOVR

TDFMO

TQRSS

TAIS

TNLOOP

TLOS

Performance

Status

PSR

R

BIST

DFMO

QRSS

AIS

NLOOP

LOS

Equalizer

Status

ESR

R

LATN7

LATN6

LATN5

LATN4

Control #4

CR4

R/W

LOS2048

1. In writable registers, bits labeled reserved should be set to 0 (except as in note 2 below) for normal operation and ignored in

read only registers.

2. Write a 1 to this bit for normal operation.