LXT362 datasheet(28/48 Pages) INTEL

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LXT362 — Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications

Datasheet

2.7.5

Other Diagnostic Reports

2.7.5.1

Receive Line Attenuation Indication

This function is only available in Host mode. The Equalizer Status Register (ESR) provides an

approximation of the line attenuation encountered by the device. The four MSBs of the register

(ESR.LATN7:4) indicate line attenuation in approximately 2.9 dB steps for the receive equalizer.

For instance, if ESR.LATN7:4 is 10 (decimal), then the receiver is seeing a signal attenuated by

approximately 29 dB (2.9 dB x 10) of cable loss.

2.7.5.2

Built-In Self Test (BIST)

The BIST function in only available in Host mode. The BIST exercises the internal circuits by

providing an internal QRSS pattern, running it through the encoders and the transmit drivers then

looping it back through the receive equalizer, jitter attenuator and decoders to the QRSS pattern

detection circuitry. The BIST is initiated by setting bit CR3.SBIST = 1. If all the blocks in this data

path operate correctly, the receive pattern detector locks onto the pattern. It then pulls INT Low and

sets the following bits:

• TSR.TQRSS = 1

• PSR.QRSS = 1

• PSR.BIST = 1

The QPD pin also indicates completion status of the test. Initiating the BIST forces QPD High.

During the test, it remains High until the test finishes successfully, at which time it goes Low.

The most reliable test will result when a separate TCLK and MCLK are applied and the Line

Build-Out (LBO) is set to -22.5 dB (CR1.EC4:1 = 011x).

LXT362 Datasheet(PDF) 28 Page - Intel Corporation