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DAC39RF10 Datasheet(PDF) 156 Page - Texas Instruments |
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DAC39RF10 Datasheet(HTML) 156 Page - Texas Instruments |
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156 / 232 page  Table 8-34. LANE_ERR[15:0] Register Field Descriptions Bit Field Type Reset Description 7-0 LANE_ERR[n] R/W1C 00h Sticky bits indicating various errors on lane n. A bit is set to indicate an error. Write a 1 to clear a bit. [7] Alignment character found at unexpected location (8b/10b) or (extended)-multi-block pilot signal not in expected location (64b/66b) [6] Multi-frame, multi-block, or extended-multi-block alignment lost. [5] Frame alignment was lost (8b/10b only) or CRC_FAULT=1 (64b/ 66b). [4] Code-group or block synchronization was lost. [3] RESERVED [2] Not-in-table or unexpected control character (8b/10b) or CRC (64b/66b) error occurred. [1] Disparity error (8b/10b) or invalid sync header (64b/66b) occurred. [0] Gearbox FIFO overflowed or underflowed. As long as the write clock frequency is correct the gearbox write clock can drift at least 3UI after this flag without causing data corruption. Note: Lane Error Flags for extra or disabled lanes are undefined. Note: LANE_ERR[6:1] are only detected for 8b/10b operation while sync_n=1 8.33 FIFO_STATUS[15:0] Register (Offset = 0170h) [Read only, reset = NA] FIFO_STATUS[15:0] is a set of 16 registers showing the status of lane n. LANE_STATUS[15:0] is shown in Figure 8-34 and described in Table 8-35. Return to the Register Summary Table. SerDes Lane n Status (n = 0 - 15). FIFO_STATUS[0] is at the lowest address. Figure 8-34. FIFO_STATUS[15:0] Register 7 6 5 4 3 2 1 0 RESERVED PDIFF[n] R-000b R Table 8-35. FIFO_STATUS[15:0] Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R 000b DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com 156 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP |
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