 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
DAC39RF10 Datasheet(PDF) 158 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
DAC39RF10 Datasheet(HTML) 158 Page - Texas Instruments |
|
|
158 / 232 page  Figure 8-36. BER_CNT Register (continued) R/W-0b Table 8-37. BER_CNT Register Field Descriptions Bit Field Type Reset Description 7-0 BER_CNT[n] R/W 0h Returns the number of bit errors detected on lane n. This value will saturate at 255. The BER for lane n can be computed as follows: BER = BER_CNT[n] / FBIT / TBER Where TBER is the number of seconds that has elapsed from when BER_EN was set to when BER_CNT[n] was read. TBER is measured by the host system or clock. Example: If BER_CNT[n] returns 2, and FBIT is 12.8Gbps, and TBER is 3600 seconds, the bit-error-rate is 2/12.8e9/3600 = 43e-15 Note: The error counters on disabled lanes and lanes enabled by EXTRA_LANE are undefined. 8.36 JPHY_CTRL Register (Offset = 01C1h) [reset = 43h] JPHY_CTRL is shown in Figure 8-37 and described in Table 8-38. Return to the Register Summary Table. JESD204C SerDes Control. Note: This register should only be changed when JESD_EN = 0. Figure 8-37. JPHY_CTRL Register 7 6 5 4 3 2 1 0 RESERVED CDR RESERVED OC_EN LOS_EN R/W-0b R/W-100b R/W-0b R/W-1b R/W-1b Table 8-38. JPHY_CTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0b 6-4 CDR R/W 100b Control CDR (clock-data-recovery) setting. The default value should be appropriate, but other settings can be used to adjust the tracking rate or reduce CDR power consumption. The 2nd order modes are for tracking a frequency offset when the Tx and Rx do not share a common reference clock. This is not applicable to JESD204C. See CDR Settings. 3-2 RESERVED R/W 00b 1 OC_EN R/W 1b Enable offset compensation/calibration for all lanes. 0 LOS_EN R/W 1b Enable loss-of-signal detector for all lanes. Table 8-39. CDR Settings CDR Vote Threshold Tracking Rate [ppm] Order Settling Time [UI] Activity % 0 15 313 2nd 36 83 1 7 607 2nd 36 70 2 3 723 2nd 36 50 3 1 868 2nd 36 25 4 (default) 15 96 1st 36 83 5 3 289 1st 36 50 6 1 434 1st 36 25 DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com 158 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
