DAC39RF10 datasheet(157/232 Pages) TI2

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Table 8-35. FIFO_STATUS[15:0] Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

4-0

PDIFF[n]

This register returns the difference between the write and read

pointers inside the gearbox FIFO for logical lane n.

For 8b/10b, values from 0-14 will be returned. For 64b/66b, values

from 0-16 will be returned.

The values at the ends of the range (0 & 14 for 8b/10b or 0 &

16 for 64b/66b) indicate error positions that will cause the Gearbox

FIFO overflow/underflow flag to be set in LANE_ERR. In both cases,

1 indicates minimum setup and the max value minus 1 indicates

minimum hold.

Values are measured in the read clock. The tread size is

approximately ½ of the effective link layer clock period (0.5/

(LCR*FDR)). In terms of UI:

•

In 8b/10b mode, the nominal tread size is 20UI. The nominal

tread size for the final tread (14) is 380UI±20UI.

•

In 64b/66b mode, the nominal tread size is 16.5UI. The nominal

tread size for the final tread (16) is 412.5UI±16.5UI.

The PDIFF[n] value for disabled lanes and lanes enabled by

EXTRA_LANE are undefined.

8.34 BER_EN Register (Offset = 01A0h) [reset = 00h]

BER_EN is shown in Figure 8-35 and described in Table 8-36.

Return to the Register Summary Table.

BER Measurement Control

Figure 8-35. BER_EN Register

RESERVED

BER_EN

R/W-0b

Table 8-36. BER_EN Register Field Descriptions

Bit

Field

Type

Reset

Description

7-1

RESERVED

R/W

00h

BER_EN

R/W

BER (bit-error-rate) test enable. After setting up the receiver

parameters, the user can program JTEST to a PRBS mode, set

JESD_EN, and then set BER_EN to enable the BER counters (see

BER_CNTn). To clear and restart the counters, program BER_EN

to 0 and then back to 1. The BER logic will self-synchronize to the

incoming PRBS data after the rising edge of BER_EN.

8.35 BER_CNT Register (Offset = 01B0h) [reset = NA, read rnly]

BER_CNT is shown in Figure 8-36 and described in Table 8-37.

Return to the Register Summary Table.

BER Error Count for Lane n. Lane 0 is a the lowest address

Figure 8-36. BER_CNT Register

BER_CNT[n]

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DAC39RF10-SP, DAC39RF10-SEP

DAC39RFS10-SP, DAC39RFS10-SEP

SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026

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