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DAC39RF10 Datasheet(PDF) 159 Page - Texas Instruments |
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DAC39RF10 Datasheet(HTML) 159 Page - Texas Instruments |
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159 / 232 page  Table 8-39. CDR Settings (continued) CDR Vote Threshold Tracking Rate [ppm] Order Settling Time [UI] Activity % 7 7 13 1st 1524 5 8.37 EQ_CTRL Register (Offset = 01C2h) [reset = 00h] EQ_CTRL is shown in Figure 8-38 and described in Table 8-40. Return to the Register Summary Table. SerDes Equalizer Control Figure 8-38. EQ_CTRL Register 7 6 5 4 3 2 1 0 RESERVED EQ_OVR EQZ_OVR EQHLD EQMODE R/W-000b R/W-0b R/W-0b R/W-0b R/W-00b Table 8-40. EQ_CTRL Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 000b 4 EQ_OVR R/W 0b When EQMODE=1, you can program EQ_OVR=1 to over-ride the equalizer level using the EQLEVEL[n] registers. Affects all lanes. 3 EQZ_OVR R/W 0b Set this bit to enable the EQZERO register (to override the equalizer’s zero frequency). When EQZ_OVR=0, the frequency is set based on the RATE register. Affects all lanes. 2 EQHLD R/W 0b When the equalizer is in fully-adaptive mode (EQMODE=1 and EQ_OVR=0), programming EQHLD will freeze (hold) the adaptation loop (for all lanes). 1-0 EQMODE R/W 00b Sets the equalizer mode (for all lanes): See Equalizer. 0: Equalizer disabled. Flat response with maximum gain. 1: Equalizer enabled. The equalizer is fully adaptive if EQ_OVR=0. 2: Precursor equalization analysis. 3: Postcursor equalization analysis. 8.38 EQZERO Register (Offset = 01C3h) [reset = 00h] EQZERO is shown in Figure 8-39 and described in Table 8-41. Return to the Register Summary Table. SerDes Equalizer Zero. Figure 8-39. EQZERO Register 7 6 5 4 3 2 1 0 RESERVED EQZERO R/W-000b R/W-00h Table 8-41. EQZERO Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 000b www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 159 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP |
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