DAC39RF10 datasheet(111/232 Pages) TI2

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The method used for NCO synchronization is controlled through the register setting.

The JESD204C LSB approach allows the synchronization information to be embedded in the input data and can

therefore be easily controlled by the data source (that is, FPGA). By controlling the timing of the synchronization

bit across multiple devices, multi-device synchronization can be achieved.

Synchronization by issuing a SYSREF pulse requires a DC coupled SYSREF interface and the ability to issue a

single SYSREF pulse unless the NCO frequency is an integer multiple of the SYSREF frequency. Many systems

will use AC coupled SYSREF signals which eliminates the ability to reliably issue a single SYSREF pulse.

Careful timing of the SPI interface, especially for very slow SYSREF signals (< 10 MHz), may make masking

and unmasking of SYSREF at multiple devices possible, however it is not characterized since the SPI path is

asynchronous.

With SPI_SYNC synchronization, all NCOs within the device can be updated simultaneously.

7.3.6.1.2.4.1 JESD204C LSB Synchronization

The NCO blocks can be synchronized using the LSB of the "I" input of the DUC0 channel on the JESD204C

interface in complex input JMODES. Control bits that replace the LSB of the data samples are used to reset the

NCO phase or an NCO frequency change. Table 7-11 show how the SYNC bit replaces the I sample LSB when

using LSB replacement. The LSB replacement mode is enabled when the SPI_SYNC register bit is high while

NCO_SYNC_SRC is set to 3. To trigger the event, the LSB must be low for 4 or more consecutive samples, and

then high for 4 consecutive samples. The sync coincides with the 4th high sample arriving at the DUC0 input.

When using the SPI to update the NCO frequency word, the user must set SPI_SYNC back to 0 to change back

to the LSB representing I sample data. When using the FR interface to update the NCO, the LSB changes back

to representing the I sample data after the synchronization event is triggered.

Table 7-11. Bit Assignment using LSB Replacement

BIT

I Sample

I[15:1]

Sync

Q Sample

Q[15:0]

7.3.6.1.2.5 NCO Mode Programming

Table 7-13 and Table 7-12 show the register programming for the different NCO modes. Each NCO[n] can have

separate mode selection.

Table 7-12. NCO Programming: SPI Usage (FR_EN = 0)

NCO_AR[n]

NCO_CONT[n]

Mode

Phase Coherent

Phase Continuous

Phase Reset

Table 7-13. NCO Programming: FRI Usage (FR_EN = 1)

FR_NCO_AR[n]

NCO_CONT[n]

Mode

Phase Coherent

Phase Continuous

Phase Reset

7.3.6.1.3 Mixer Scaling

The DUC mixer support complex to complex or complex to real mixing of the complex interpolated input signal

with the NCO frequency. The scaling in the mixer is exactly 1:1, so a fullscale 16-bit (absolute amplitude =

32767) complex tone results in a fullscale real or complex tone at the output. If the input absolute value of the

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DAC39RF10-SP, DAC39RF10-SEP

DAC39RFS10-SP, DAC39RFS10-SEP

SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026

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