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DAC39RF10 Datasheet(PDF) 114 Page - Texas Instruments |
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DAC39RF10 Datasheet(HTML) 114 Page - Texas Instruments |
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114 / 232 page ![]() Normalized Frequency (/FCLK) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 DES2XL DES2XH Figure 7-48. DES Interpolator Frequency Response Normalized Frequency (/FCLK) 0 0.04 0.08 0.12 0.16 0.2 0.24 0.28 0.32 0.36 0.4 -0.1 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.1 Figure 7-49. DES Interpolator Frequency Response (Passband) 7.3.7 JESD204C Interface The devices uses a JESD204C high-speed serial interface to transfer data from the logic device to the receiving DAC. The device serial lanes are capable of operating with both 8b/10b encoding and 64b/66b encoding. The JESD204C formats using 8b/10b encoding are backwards compatible with existing JESD204B receivers. A maximum of 16 lanes can be used to lower lane rates for interfacing with speed limited logic devices. There are a few differences between 8b/10b and 64b/66b encoding, which is highlighted throughout this section. Figure 7-50 shows a simplified block diagram of the 8b/10b encoded JESD204C interface and Figure 7-51 shows a simplified block diagram of the 64b/66b encoded JESD204C interface. DAC TRANSPORT LAYER SCRAMBLER (Optional) SERDES TX PHY 8b/10b LINK LAYER APPLICATION LAYER TRANSPORT LAYER DESCRAMBLE (Optional) SERDES RX PHY 8b/10b LINK LAYER Logic Device JESD204B or JESD204C Block DAC Device JESD204C Block ANALOG CHANNEL Figure 7-50. Simplified JESD204C Interface Diagram with 8b/10b Encoding DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com 114 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP |
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