DAC39RF10 datasheet(116/232 Pages) TI2

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Table 7-16. Summary of JESD204C Signals (continued)

SIGNAL NAME

DEVICE PIN NAMES

DESCRIPTION

SYNC

Link initialization signal (handshake),

toggles low to start code group

synchronization (CGS) process. Not

used for 64B/66B encoding modes.

Device clock

CLK+, CLK–

DAC sampling clock, also used for

clocking digital logic and SerDes

receivers.

SYSREF

SYSREF+, SYSREF–

System timing reference used to

deterministically reset the internal local

multiframe clock (LMFC) or local

extended multiblock clock (LEMC)

counters in each JESD204C device

7.3.7.1 Deviation from JESD204C Standard

JESD204C section 4.3.4 requires subclass 1 devices to be able to measure the amount of device clock cycles

by which the detected active edge of the SYSREF signal deviates from its expected position and not to re-align

the LMFC/LEMC if the deviation from the expected position is less than a programmable number of device clock

cycles. This design does not contain this feature, but is compliant with JESD204B in this regard. The LMFC

and other supporting clocks are aligned to the detected SYSREF if the JESD204C subsystem and SYSREF

processor are enabled (and SYSREF_ALIGN_EN=1).

7.3.7.2 Transport Layer

In the transmitter (logic device) the transport layer takes samples from the application layer and maps the

samples into octets inside of frames. The frames are then mapped onto the available SerDes lanes. In the

receiver (DAC) the transport layer performs the inverse operation to extract samples from the serialized data.

The mapping of octets into frames and frames onto lanes is defined by the transport layer settings such as L,

M, F, S, N and N'. An octet is 8 bits (before 8b/10b or 64b/66b encoding), a frame consists of F octets and the

frames are mapped onto L lanes. Samples are N bits, but sent as N' bits across the link. The samples come from

M converters and there are S samples per converter per frame cycle.

There are a number of predefined transport layer modes in the device that are defined in JESD204C

Interface Modes. The various configuration parameters for JESD204C block are defined in JESD204C Interface

Parameter Definitions.

The link layer further maps the frames into multiframes.

7.3.7.3 Scrambler and Descrambler

A data descrambler is available in the DAC device to descramble the data after reception. Scrambling is

used to remove the possibility of spectral peaks in the transmitted data due to repetitive data streams. The

scrambler is optional for 8b/10b encoded mode, however it is mandatory for 64b/66b encoded mode to

have sufficient spectral content for clock recovery and adaptive equalization. The scrambler operates on the

data before encoding, such that the 8b/10b scrambler scrambles the 8-bit octets before 10-bit encoding and

the 64b/66b scrambler scrambles the 64-bit block before the sync header insertion (66-bit encoding). The

JESD204C receiver automatically synchronizes its descrambler to the incoming scrambled data stream. For

8b/10b encoding, the initial lane alignment sequence (ILAS) is never scrambled. The descrambler can be

enabled by setting SCR for 8b/10b encoding mode, but it is automatically enabled in 64b/66b mode. The

scrambling polynomial is different for 8b/10b encoding and 64b/66b encoding schemes as defined by the

JESD204C standard.

7.3.7.4 Link Layer

The link layer serves multiple purposes in JESD204C for both 8b/10b and 64b/66b encoding modes,

however there are some differences in implementation for each encoding scheme. In general, the link layer

responsibilities include scrambling of the data (see Scrambler and Descrambler), establishing the code (8b/10b)

DAC39RF10-SP, DAC39RF10-SEP

DAC39RFS10-SP, DAC39RFS10-SEP

SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026

www.ti.com

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