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stretches from the minimum to maximum delay for all lanes. Essentially, the designer must make sure that the

data for all lanes arrives at all devices after the previous release point occurs and before the next release point

occurs. The invalid region can also be found experimentally - see Programming RBD.

Figure 7-54 provides a simplified timing diagram that demonstrates this requirement. In this figure, the data for

two transmitters (ADC or logic device) is shown. The second transmitter (TX 2) has a longer routing distance

(tPCB) and results in a longer link delay than the first transmitter (TX 1). First, the invalid region of the LMFC

period is marked off as determined by the data arrival times for all devices. Then, the release point is set by

using the release buffer delay (RBD) parameter to shift the release point an appropriate number of quad-octet

steps from the LMFC edge so that the release point occurs within the valid region of the LMFC cycle. In the

case of Figure 7-54, the LMFC edge (RBD = 0) is a good choice for the release point because there is sufficient

margin on each side of the valid region.

TX LMFC/LEMC

RX LMFC/LEMC

TX 1 Data

Propagation

PCB

RX-DESER

Time

TX 2 Data

Propagation

PCB

Invalid Region

of LMFC/LEMC

Valid Region of

LMFC/LEMC

Nominal Link Delay

(Arrival at Elastic Buffer)

Link Delay

Variation

Choose LMFC/LEMC

edge as release point

(RBD = 0)

Release point

margin

RX-DESER

Figure 7-54. LMFC Valid Region Definition for Elastic Buffer Release Point Selection

The TX and RX LMFC do not necessarily need to be phase aligned, but knowledge of their phase is important

for proper elastic buffer release point selection. Also, the elastic buffer release point occurs within every LMFC

cycle, but the buffers only release when all lanes have arrived. Therefore, the total link delay can exceed a

single LMFC period; see JESD204B multi-device synchronization: Breaking down the requirements for more

information.

7.3.7.8.1 Programming RBD

The range of values for RBD depends on the phase delta between the Rx and Tx LMFC/LEMC, as well as link

latencies in the Tx, channel, and Rx. Therefore, do not provide a pre-determined RBD value that is appropriate

for all systems. The LANE_ARR registers are provided to help the user measure lane arrival times and select an

appropriate RBD value for the system. For deterministic latency, the RBD value can be selected during system

prototyping and stored in system firmware. Calculating RBD each time the system is turned on can result in

non-deterministic latency.

The arrival times are reported in units of quad-bytes and are measured with respect to a modulo-64 reference

counter that increments for each quad-byte received (per lane). The reference counter is aligned (reset) by

SYSREF.

Since the lane arrival times are modulo-values, it is important to use arithmetic that accounts for the modulus

(the latest arriving lane might actually have a smaller LANE_ARR value than the earliest arriving lane). Figure

7-55 and Figure 7-56 depict the RBD calculation graphically to emphasize this. The lane arrival times are

mapped onto a circle with a circumference of 64 quad-bytes which corresponds to the modulo-64 counter used

to measure lane arrival times.

The earliest usable RBD value is equal to the latest LANE_ARR value plus 1 (modulo 64). The latest usable

RBD value is equal to the earliest LANE_ARR value plus the buffer depth (modulo 64) (the buffer depth is 16

quad-octets, except when K x F = 32, then the buffer depth is reduced to 8 quad-octets). Note that the latest,

DAC39RF10-SP, DAC39RF10-SEP

DAC39RFS10-SP, DAC39RFS10-SEP

SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026

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