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DAC39RF10 Datasheet(PDF) 123 Page - Texas Instruments

Part # DAC39RF10
Description  DAC39RFx10-SP DAC39RFx10-SEP 10.4 or 20.8GSPS, 16-bit, Dual and Single Channel, Multi-Nyquist Digital-to-Analog Converter (DAC) with JESD204C Interface
PDF  232 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
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DAC39RF10 Datasheet(HTML) 123 Page - Texas Instruments

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7.4.2 JESD204C Interface Modes
Each operational mode has a limited set of available interface formats (number of lanes, resolution).
7.4.2.1 JESD204C Interface Modes
The device JESD204C modes are configured with the parameters defined in Table 7-19, Table 7-20 and Table
7-21.
Table 7-19. JESD204C Interface Parameter Definitions
Parameter
Description
JMODE
JESD204C mode number. The user configures this parameter to choose a supported mode. Most other parameters
are derived from this setting. See Table 7-22.
LS
Lanes per sample stream. This is derived from JMODE. See Table 7-22.
LT
Ratio of clock to input sample rate. LT = FCLK / FINPUT. A value of 0.5 indicates that the DES1X mode is enabled,
and the input sampling rate is twice the DAC clock frequency (the JESD204C system provides two samples per
CLK cycle). If DES1X mode is not enabled, LT equals the interpolation factor, the ratio of output to input sample
rate. Not that DES2X mode does not affect the value of LT.
Interpolation factor 1-256x is programmed in the DUC_L register.
Lx
Maximum number of lanes used for a given JMODE. The link scales down the number of active lanes (L) depending
on how many channels are enabled. See JESD_M register.
Mx
Maximum number of streams for a given JMODE. Mx is computed automatically according to Table 7-22. The user
can specify the actual number of streams (M) using the JESD_M register.
R
Number of bits transmitted per lane per CLK cycle. Derived from JMODE and LT (see Table 7-22). Based on R, the
user must program REFDIV, MPY, and RATE registers. Additionally, the maximum CLK frequency is a function of R.
SI
Sample Interleaving/Increment Factor. A value of 1 indicates that the standard transport layer mapping from the
JESD204C standard is used (samples are mapped linearly from 0 to S-1). A value greater than 1 indicates that an
alternate mapping is used as follows: Map samples starting with sample 0, incrementing the index by SI. Repeat this
as many times as necessary to map all S samples, starting each repetition at an index that is one larger than the
previous repetition. See JESD Format Diagrams JESD Format Diagrams.
KR
For 8b/10b operation, KR defines the legal values of K (frames per multiframe). The legal values are restricted
to facilitate upset immunity of the elastic buffer. The multiframe length is restricted to a multiple of the elastic
buffer depth of 64 characters (buffer depth is reduced to 32 characters if K=32 and F=1). For 8b/10b modes, K is
programmed via the KM1 register.
www.ti.com
DAC39RF10-SP, DAC39RF10-SEP
DAC39RFS10-SP, DAC39RFS10-SEP
SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026
Copyright © 2026 Texas Instruments Incorporated
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Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP



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