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DAC39RF10 Datasheet(PDF) 125 Page - Texas Instruments

Part # DAC39RF10
Description  DAC39RFx10-SP DAC39RFx10-SEP 10.4 or 20.8GSPS, 16-bit, Dual and Single Channel, Multi-Nyquist Digital-to-Analog Converter (DAC) with JESD204C Interface
PDF  232 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

DAC39RF10 Datasheet(HTML) 125 Page - Texas Instruments

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Table 7-22. JESD Interface Modes
JMODE
Encoding Max Input
Sample
Rate per
Stream
(MSPS)
MAX
Serdes
Baud
Rate
(Gbps)
R =
FBIT/ FCLK
N
Mx = Max
#
Streams
Ls =
Lanes/
Stream
Lx = Max
# Lanes
LT =
Interpolation
JESD Format
KR
MIN
MAX
F
S
HD SI
0
8b/10b
10240
12.8
1.25
16
1
16
16
1
1
2
16
0
1
32, 64,
128
64b/66b
10400
10.725
1.03125
1
8b/10b
5120
12.8
2.5/LT
16
2
8
16
1
8
2
8
0
1
32, 64,
128
64b/66b
6206.1
12.8
2.0625/LT
2
8b/10b
2560
12.8
5/LT
16
4
4
16
1
16
2
4
0
1
32, 64,
128
64b/66b
3103.0
12.8
4.125/LT
3
8b/10b
1280
12.8
10/LT
16
8
2
16
2
32
2
2
0
1
32, 64,
128
64b/66b
1551.5
12.8
8.25/LT
4
8b/10b
640
12.8
20/LT
16
8
1
8
4
64
2
1
0
1
32, 64,
128
64b/66b
775.8
12.8
16.5/LT
5
8b/10b
320
12.8
40/LT
16
8
½
4
8
128
4
1
0
1
16,32,64
64b/66b
387.9
12.8
33/LT
6
8b/10b
160
12.8
80/LT
16
8
¼
2
16
256
8
1
0
1
8,16,32
64b/66b
193.9
12.8
66/LT
7
8b/10b
80
12.8
160/LT
16
8
⅛
1
32
256
16
1
0
1
4,8,16
64b/66b
97.0
12.8
132/LT
8
8b/10b
12800
12.8
1/LT
12
1
16
16
0.5
1
8
80
0
16
8,16,32
64b/66b
15515.2
12.8
0.825/LT
9
8b/10b
9600
12.8
1.25
12
1
12
12
1
1
2
16
1
1
32,64,
128
64b/66b
10400
10.725
1.03125
10
8b/10b
6400
12.8
2
12
2
8
16
1
1
8
40
0
8
8,16,32
64b/66b
7757.6
12.8
1.65
11
8b/10b
4800
12.8
2.5
12
2
6
12
1
1
2
8
1
1
32,64,
128
64b/66b
6206.1
12.8
2.0625
12
8b/10b
3200
12.8
4
12
2
4
8
1
1
8
20
0
4
8,16,32
64b/66b
3878.8
12.8
3.3
13
8b/10b
2400
12.8
5
12
2
3
6
1
1
2
4
1
1
32,64,
128
64b/66b
3103.0
12.8
4.125
14
8b/10b
20480
12.8
0.625/LT
8
1
16
16
0.5
1
1
16
0
1
32,64,
128,256
64b/66b
20800
10.725
0.515625/LT
15
8b/10b
10240
12.8
1.25
8
2
8
16
1
1
1
8
0
1
32,64,
128,256
64b/66b
10400
10.725
1.03125
16
8b/10b
5120
12.8
2.5
8
2
4
8
1
1
1
4
0
1
32,64,
128,256
64b/66b
6206.1
12.8
2.0625
1. At minimum interpolation rate
7.4.2.2 JESD204C Format Diagrams
The following sub-sections depict each output format, showing how samples and tail bits are mapped to the
lanes. Any lanes that are not shown in the output format tables are unused. Each table depicts exactly one
frame. Tail bits are discarded and ignored by the transport layer. All diagrams are with respect to the logical lane
numbers which can be arbitrarily mapped to the external physical lanes using LANE_SELn.
Table 7-23. Format Notation Description
Notation
Description
T
Tail bits (used for some 12-bit modes)
CH0_I[n]
In-Phase samples for channel 0. Can also be considered as “channel A” when the input isn’t considered to be
complex data.
www.ti.com
DAC39RF10-SP, DAC39RF10-SEP
DAC39RFS10-SP, DAC39RFS10-SEP
SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026
Copyright © 2026 Texas Instruments Incorporated
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Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP



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