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DAC39RF10 Datasheet(PDF) 121 Page - Texas Instruments |
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DAC39RF10 Datasheet(HTML) 121 Page - Texas Instruments |
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121 / 232 page ![]() usable RBD value causes the earliest arriving lane to overwrite buffer data on the same clock cycle that the data is being read out (this is acceptable and does not cause overflow). Choosing an RBD value in the middle of the usable range maximizes the skew tolerance; however, the user can choose a value closer to the latest arriving lane if lower latency is desired. Figure 7-55. RBD Example (lane arrivals do not straddle zero) Figure 7-56. RBD Example (lane arrivals straddle zero) 7.3.7.9 Operation in Subclass 0 Systems The device can operate with subclass 0 compatibility provided that multi-DAC synchronization and deterministic latency are not required. With these limitations, the device can operate without the application of SYSREF. The internal LMFC is automatically self-generated with unknown starting phase. RBD does not need to be programmed as the elastic buffer is released automatically just after the latest arriving lane begins to write to the elastic buffer. SYNC is used as normal to initiate the CGS and ILAS. 7.3.7.10 Link Reset The entire link layer for all lanes is reset any time: • There is a gearbox FIFO underflow/overflow detected (LANE_ERR[0]) on a lane used by the JESD link • There is an elastic buffer overflow detected (EB_ERR) on a lane used by the JESD link • The JESD link goes down (JESD_LINK_DOWN_ALM) • SYSREF causes clock divider or LMFC/LEMC realignment (REALIGNED) • The JTimer expires (JTIMER_EXPIRED_ALM) 7.3.8 Alarm Generation The alarm pin is useful for notifying the host controller of events that may require intervention. Any active alarms in the SYS_ALM register asserts the alarm output if they are not masked in the ALM_MASK register. 7.4 Device Functional Modes This section describes the functional modes of the device. Some of the features in this section have been discussed in further detail in Feature Description. www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 121 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP |
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