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DAC39RF10 Datasheet(PDF) 119 Page - Texas Instruments |
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DAC39RF10 Datasheet(HTML) 119 Page - Texas Instruments |
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119 / 232 page  Table 7-18. PLL Configuration Table for 64b/66b Encoding Modes R decimal (fraction) CLK Range (FCLK) (GHz) Register Values to Program Actual Frequency Multipliers Lane Bit Rate (FBIT) (Gbps) REFDIV MPY RATE VRANGE REFDIV MPY RATE 0.515625 (33/64) 6.06 – 12.41 0x20 0x21 0x1 FCLK<8.417GHz 1/32 8.25 2 3.125 – 6.4 0.6875 (33/48) 4.55 – 9.31 0x18 0x21 0x1 FCLK<6.313GHz 1/24 8.25 2 3.125 – 6.4 0.6875 (33/48) 9.09 – 12.8 0x30 0x21 0x0 FCLK<12.625GHz 1/48 8.25 4 6.25 – 8.8 0.825 (33/40) 3.79 – 7.76 0x14 0x21 0x1 FCLK<5.261GHz 1/20 8.25 2 3.125 – 6.4 0.825 (33/40) 7.58 – 12.8 0x28 0x21 0x0 FCLK<10.521GHz 1/40 8.25 4 6.25 – 10.56 1.03125 (33/32) 3.03 – 6.21 0x10 0x21 0x1 FCLK<4.208GHz 1/16 8.25 2 3.125 – 6.4 1.03125 (33/32) 6.06 – 12.41 0x20 0x21 0x0 FCLK<8.417GHz 1/32 8.25 4 6.25 – 12.8 1.375 (33/24) 2.27 – 4.65 0x0C 0x21 0x1 FCLK<3.156GHz 1/12 8.25 2 3.125 – 6.4 1.375 (33/24) 4.55 – 9.31 0x18 0x21 0x0 FCLK<6.313GHz 1/24 8.25 4 6.25 – 12.8 1.65 (33/20) 1.89 – 3.88 0x0A 0x21 0x1 FCLK<2.630GHz 1/10 8.25 2 3.125 – 6.4 1.65 (33/20) 3.79 – 7.76 0x14 0x21 0x0 FCLK<5.261GHz 1/20 8.25 4 6.25 – 12.8 2.0625 (33/16) 1.52 – 3.10 0x08 0x21 0x1 FCLK<2.104GHz 1/8 8.25 2 3.125 – 6.4 2.0625 (33/16) 3.03 – 6.21 0x10 0x21 0x0 FCLK<4.208GHz 1/16 8.25 4 6.25 – 12.8 2.75 (33/12) 1.14 – 2.33 0x06 0x21 0x1 FCLK<1.578GHz 1/6 8.25 2 3.125 – 6.4 2.75 (33/12) 2.27 – 4.65 0x0C 0x21 0x0 FCLK<3.156GHz 1/12 8.25 4 6.25 – 12.8 3.3 (33/10) 0.95 – 1.94 0x05 0x21 0x1 FCLK<1.315GHz 1/5 8.25 2 3.125 – 6.4 3.3 (33/10) 1.89 – 3.88 0x0A 0x21 0x0 FCLK<2.630GHz 1/10 8.25 4 6.25 – 12.8 4.125 (33/8) 0.76 – 1.55 0x04 0x21 0x1 FCLK<1.052GHz 1/4 8.25 2 3.125 – 6.4 4.125 (33/8) 1.52 – 3.10 0x08 0x21 0x0 FCLK<2.104GHz 1/8 8.25 4 6.25 – 12.8 7.3.7.7 Serdes Crossbar The device includes a crossbar immediately after coming out of the PHY that allows mapping of signals between lanes to simplify PCB routing between the Tx and Rx which could save PCB complexity or shorten the traces (reduce loss). See LANE_SEL n . The physical layer lanes (0SRX± to 15SRX±) must be routed to the appropriate JESD204C lanes (JESD0 to JESD15) based on the lanes defined in the bit packing diagrams shown in JESD204C Format Diagrams. Crossbar 0SRX+ 0SRX– 15SRX+ 15SRX– JESD204C 0SRX 15SRX JESD0 JESD15 Figure 7-53. Crossbar Block Diagram 7.3.7.8 Multi-Device Synchronization and Deterministic Latency JESD204C subclass 1 outlines a method to achieve deterministic latency across the serial link. If two devices achieve the same deterministic latency then the devices are considered synchronized. This latency must be achieved from system startup to startup to be deterministic. There are two key requirements to achieve deterministic latency. The first is proper capture of SYSREF. SYSREF resets the LMFC counter in each device to act as a known timing reference. The second requirement is to choose a proper elastic buffer release point in the receiver. The converter device is the receiver (RX) in the JESD204C link and the logic device is the transmitter (TX). The elastic buffer is the key block for achieving deterministic latency and does so by absorbing variations in the propagation delays of the serialized data as the data travels from the transmitter to the receiver. A proper release point is one that provides sufficient margin against delay variations. Choosing a proper release point requires knowing the average arrival time of data at the elastic buffer, referenced to an LMFC edge, and the total expected delay variation for all devices. With this information the region of invalid release points within the LMFC period can be defined, which www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 119 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP |
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