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DAC39RF10 Datasheet(PDF) 132 Page - Texas Instruments

Part # DAC39RF10
Description  DAC39RFx10-SP DAC39RFx10-SEP 10.4 or 20.8GSPS, 16-bit, Dual and Single Channel, Multi-Nyquist Digital-to-Analog Converter (DAC) with JESD204C Interface
PDF  232 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

DAC39RF10 Datasheet(HTML) 132 Page - Texas Instruments

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7.4.3 NCO Synchronization Latency
There are two deterministic methods for synchronizing the NCO (frequency or phase change, accumulator
reset): through an LSB of the JESD204C interface or via SYSREF. The latency parameters for each
sychronization method are listed in Table 7-41.
Using SYSREF as the Synchronization source, the latency parameter TSYSREF_NCO is the time between the
moment SYSREF is sampled high by CLK and the arrival of the NCO change at the DAC output. The alignment
to the data path samples can be calculated by the Excel spreadsheet latency calculator discussed in Section
7.4.4.
When using the JESD204C interface LSB, the latency parameter TJSYNC_NCO is the difference in time of the
NCO synchronization event relative to the corresponding data sample aligned with the LSB. TJSYNC_NCO is
deterministic, but for some modes depends on the alignment of the LSB rising edge to the multiframe boundary
(see Table 7-42).
Table 7-41. NCO Synchronization Latency Parameters
Latency Parameter
Description
Value
TSYSREF_NCO
Latency from SYSREF sampled high (by CLK) to DAC output reacting to an NCO
synchronization event (that was triggered by SYSREF).
477.5 CLK cycles
TJSYNC_NCO
The latency through the interpolation filter(s) to the NCO minus the latency of the
LSB that synchronizes the NCO. Applies only when using the LSB of the input data
to synchronize the NCO. To make input sample n be the first sample to be mixed
with a new NCO frequency or phase, the LSB should be brought high on sample n’
= n+TJSYNC_NCO/LT. Note that n’ may not be an integer as the synchronization path
is not always a whole number of input sample periods.
See Table 7-42
Table 7-42. TJSYNC_NCO vs. LT
Interpolation Factor (LT)
TJSYNC_NCO [CLK cycles](1)
2
-144, -142, -140, -138, -136, -134, -132, -130
3
-89, -86, -83, -81, -80, -78, -77, -75, -74, -72, -71, -69, -68, -66, -63, -60
4
-36, -32, -28, -24
6
34, 40, 42, 46, 48, 52, 54, 60
8
86, 94
12
186, 194, 198, 206
16
290
24
458, 466
32
648
48
968
64
1396
96
2036
128
2932
192
4212
256
6004
(1)
When multiple values are listed, it indicates that TJSYNC_NCO depends on when the LSB rises with respect to the multiframe boundary.
7.4.4 Data Path Latency
There are several difference latencies defined for the device as shown in Figure 7-57 and listed in Table 7-43.
The latency within the device is dependent on the mode of operation, including JMODE, Interpolation factor,
RBD setting, NCO usage and DES setting. An Excel spreadsheet calculator is provided by TI to calculate the
device latency in different modes of operation.
In JESD204C subclass 0 operation, the latency from Serdes input to DAC output is called TDAC_LAT0 and is not
deteriministic and a minimum and maximum range is provided in the Excel spreadsheet calculator.
DAC39RF10-SP, DAC39RF10-SEP
DAC39RFS10-SP, DAC39RFS10-SEP
SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026
www.ti.com
132
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Copyright © 2026 Texas Instruments Incorporated
Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP



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