DAC39RF10 datasheet(135/232 Pages) TI2

135 / 232 page

7.5.1.6 Streaming Mode

The serial interface supports streaming reads and writes. In this mode, the initial 24 bits of the transaction

specifies the access type, register address, and data value as normal. Additional clock cycles of write or read

data are immediately transferred, as long as the SCS input is maintained in the asserted (logic low) state. The

transaction. The ASCEND bit (register 000h, bit 5) controls whether the address value ascends (increments) or

descends (decrements). Figure 7-59 shows the streaming mode transaction details.

SCLK

Multiple Register Access

SCS

SDI

Command Field

Data Field (write mode)

SDO

(read mode)

Data Field

High Z

Data Field

High Z

Data Field (write mode)

A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

R/W

D7 D6 D5 D4 D3 D2 D1 D0

Figure 7-59. Serial Interface Protocol: Streaming Read and Write

7.5.2 Using the Fast Reconfiguration Interface

The FR interface provides fast write-only access to configure NCO frequencies and synchronization. The FR

interface is similar to the SPI interface, but 4 bits are sent per clock cycle. The FR timing diagram is shown

in Figure 7-60. It uses a R/W bit (always Write for this device), a transaction sync bit (FRS), and 14-bits of

address followed by some number of data bytes. The address is decremented after each data byte (consistent

with little-endian). The interface is byte addressable and data is committed after each byte. The FR interface

is takes 4-bits (one nibble) per clock. For multi-nibble fields, data is sent most-significant nibble first. When

the transaction sync bit (FRS) is set, the synchronization event specified in the NCO_SYNC_SRC register field

occurs at the rising edge of FRCS. Transactions ended before the completion of the first data byte may not

trigger the sync event.

FRCS

FRCLK

FRDI[3]

A[11]

A[7]

A[3]

D[7]

D[3]

Address A

Address A-1

FRS

A[10]

A[6]

A[2]

D[6]

D[2]

A[13]

A[9]

A[5]

A[1]

D[5]

D[1]

A[12]

A[8]

A[4]

A[0]

D[4]

D[0]

FRDI[2]

FRDI[1]

FRDI[0]

D[7]

D[3]

D[6]

D[2]

D[5]

D[1]

D[4]

D[0]

Figure 7-60. FR Interface Timing Diagram

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DAC39RF10-SP, DAC39RF10-SEP

DAC39RFS10-SP, DAC39RFS10-SEP

SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026

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