DAC39RF10 datasheet(133/232 Pages) TI2

133 / 232 page

In JESD204C subclass 1 operation, the latency TDAC_LAT from the SYSREF input to DAC output is deterministic

and is provided in the Excel spreadsheet calculator. The JESD204C link latency is deterministic as long as

SYSREF is sampled reliably and the RBD value is set properly.

SYSREF Processor

Delay

Embed

mul frame/

EMB ming

info

PHY Layer + Link

Layer + RxFIFO setup

Scramble,

Encode,

Serialize

RxFIFO

(Hold data un l

release)

RBD Delay

SYSREF Process

Delay (TRxLMFC)

App/

Transport

Layer

RxLMFC

Release FIFO

Inequalities must me met for

deterministic link operation. Adjust

RBD to make inequalities true.

red_path(max) < blue_path + n*TMF

red_path(min) > blue_path + (n-1)*TMF

n is any integer (typically 0, 1, or 2)

TMF is the period of the multiframe/EMB

SYSREF

JESD204C Link (Determinis c Latency)

(determinis c)

(non-determinis c)

TRxIN

(determinis c)

DUC, DAC

DAC Output

TDAC_LAT

TRELEASE

PCB

Traces

Link-to-

Trans

bu er

Transport

Layer

Transport & Applica on Layer (determinis c)

JMODE,

DUC_L, RBD

DUC_L, NCO_EN,

DES2X

JMODE,

DUC_L

Delay Dependancies

TDAC_LAT0 (subclass 0 only)

Figure 7-57. Definition of Device Latencies

Table 7-43. Latency Definitions

Latency Parameter

Definition

TRELEASE

Latency from the rising edge of CLK that follows the rising edge of SYSREF to release event for elastic buffer.

(subclass 1 only).

TDAC_LAT

Latency from the rising edge of CLK that follows the rising edge of SYSREF to the time of the first sample at

the DAC output of the multiframe/extended multiblock launched by SYSREF (subclass 1 only).

TRxIN

Latency from the receiver data inputs to the elastic buffer input, including the minimum setup time of the elastic

buffer. This is non-deterministic, so a minimum and maximum limit are provided.

TDAC_LAT0

Latency from receiver data inputs (multiframe/EMB boundary) to first sample of a multiframe launched on DAC

output. This is non-deterministic, so a minimum and maximum limit are provided (subclass 0 only).

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DAC39RF10-SP, DAC39RF10-SEP

DAC39RFS10-SP, DAC39RFS10-SEP

SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026

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