DRA752ABC datasheet(148/443 Pages) TI2

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148

DRA756, DRA755, DRA754, DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F – DECEMBER 2015 – REVISED MAY 2019

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Product Folder Links: DRA756 DRA755 DRA754 DRA752 DRA751 DRA750 DRA746 DRA745 DRA744

Specifications

(1) In a typical implementation, the power supply should target the NOM voltage.

(2) The voltage at the device ball should never be below the MIN voltage or above the MAX voltage for any amount of time. This

requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, etc.

(3) The DC voltage at the device ball should never be above the MAX DC voltage to avoid impact on device reliability and lifetime POH

(Power-On-Hours). The MAX DC voltage is defined as the highest allowed DC regulated voltage, without transients, seen at the ball.

(4) For all OPPs, AVS must be enabled to avoid impact on device reliability, lifetime POH (Power-On-Hours), and device power.

(5) The AVS Voltages are device-dependent, voltage domain-dependent, and OPP-dependent. They must be read from the

STD_FUSE_OPP. For information about STD_FUSE_OPP Registers address, please refer to Control Module Section of the TRM. The

power supply should be adjustable over the following ranges for each required OPP:

–

OPP_NOM for MPU: 0.85V – 1.15V

–

OPP_NOM for CORE and Others: 0.85V - 1.15V

–

OPP_OD: 0.885V - 1.15V

–

OPP_HIGH: 0.95V - 1.25V

The AVS Voltages will be within the above specified ranges.

(6) VD_RTC can optionally be tied to VD_CORE and operate at the VD_CORE AVS voltages.

(7) The power supply must be programmed with the AVS voltages for the MPU and the CORE voltage domain, either just after the ROM

boot or at the earliest possible time in the secondary boot loader before there is significant activity seen on these domains.

Table 5-8 describes the standard processor clocks speed characteristics vs OPP of the device.

Table 5-8. Supported OPP vs Max Frequency (2)

DESCRIPTION

OPP_NOM

OPP_OD

OPP_HIGH

MAX FREQ. (MHz)

VD_MPU

MPU_CLK

1000

1176

1500

VD_DSPEVE

DSP_CLK

600

700

750

EVE_FCLK

535

650

VD_IVA

IVA_GCLK

388.3

430

532

VD_GPU

GPU_CLK

425.6

500

532

VD_CORE

CORE_IPUx_CLK

212.8

N/A

L3_CLK

266

N/A

DDR2

400 (DDR2-800)

N/A

DDR3 / DDR3L

532 (DDR3-1066)

N/A

VD_RTC

RTC_FCLK

0.034

N/A

(1) N/A in this table stands for Not Applicable.

(2) Maximum supported frequency is limited according to Table 5-5, Speed Grade Maximum Frequency).

5.5.3

Maximum Supported Frequency

Device modules either receive their clock directly from an external clock input, directly from a PLL, or from

a PRCM. Table 5-9 lists the clock source options for each module on this device, along with the maximum

frequency that module can accept. To ensure proper module functionality, the device PLLs and dividers

must be programmed not to exceed the maximum frequencies listed in this table.

Table 5-9. Maximum Supported Frequency

Module

Clock Sources

Instance Name

Input Clock Name

Clock

Type

Max. Clock

Allowed (MHz)

PRCM Clock Name

PLL / OSC /

Source Clock

Name

PLL / OSC /

Source Name

AES1

AES1_L3_CLK

Int

266

L4SEC_L3_GICLK

CORE_X2_CLK

DPLL_CORE

DRA752ABC Datasheet(PDF) 148 Page - Texas Instruments

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