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DRA752ABC Datasheet(PDF) 149 Page - Texas Instruments |
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DRA752ABC Datasheet(HTML) 149 Page - Texas Instruments |
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149 / 443 page  149 DRA756, DRA755, DRA754, DRA752 DRA751, DRA750, DRA746, DRA745, DRA744 www.ti.com SPRS950F – DECEMBER 2015 – REVISED MAY 2019 Submit Documentation Feedback Product Folder Links: DRA756 DRA755 DRA754 DRA752 DRA751 DRA750 DRA746 DRA745 DRA744 Specifications Copyright © 2015–2019, Texas Instruments Incorporated Table 5-9. Maximum Supported Frequency (continued) Module Clock Sources Instance Name Input Clock Name Clock Type Max. Clock Allowed (MHz) PRCM Clock Name PLL / OSC / Source Clock Name PLL / OSC / Source Name AES2 AES2_L3_CLK Int 266 L4SEC_L3_GICLK CORE_X2_CLK DPLL_CORE ATL ATL_ICLK_L3 Int 266 ATL_L3_GICLK CORE_X2_CLK DPLL_CORE ATLPCLK Func 266 ATL_GFCLK CORE_X2_CLK DPLL_CORE PER_ABE_X1_GF CLK DPLL_ABE FUNC_32K_CLK OSC1 RTC Oscillator VIDEO1_CLK DPLL_VIDEO1 VIDEO2_CLK DPLL_VIDEO2 HDMI_CLK DPLL_HDMI BB2D BB2D_FCLK Func 354.6 BB2D_GFCLK BB2D_GFCLK DPLL_CORE BB2D_ICLK Int 266 DSS_L3_GICLK CORE_X2_CLK DPLL_CORE COUNTER_32K COUNTER_32K_F CLK Func 0.032 FUNC_32K_CLK SYS_CLK1/610 OSC1 COUNTER_32K_IC LK Int 38.4 WKUPAON_GICLK SYS_CLK1 OSC1 DPLL_ABE_X2_CL K DPLL_ABE CTRL_MODULE_B ANDGAP L3INSTR_TS_GCL K Int 4.8 L3INSTR_TS_GCLK SYS_CLK1 OSC1 DPLL_ABE_X2_CL K DPLL_ABE CTRL_MODULE_C ORE L4CFG_L4_GICLK Int 133 L4CFG_L4_GICLK CORE_X2_CLK DPLL_CORE CTRL_MODULE_ WKUP WKUPAON_GICLK Int 38.4 WKUPAON_GICLK SYS_CLK1 OSC1 DPLL_ABE_X2_CL K DPLL_ABE DCAN1 DCAN1_FCLK Func 38.4 DCAN1_SYS_CLK SYS_CLK1 OSC1 SYS_CLK2 OSC2 DCAN1_ICLK Int 266 WKUPAON_GICLK SYS_CLK1 OSC1 DPLL_ABE_X2_CL K DPLL_ABE DCAN2 DCAN2_FCLK Func 38.4 DCAN2_SYS_CLK SYS_CLK1 OSC1 DCAN2_ICLK Int 266 L4PER2_L3_GICLK CORE_X2_CLK DPLL_CORE DES3DES DES_CLK_L3 Int 266 L4SEC_L3_GICLK CORE_X2_CLK DPLL_CORE DLL EMIF_DLL_FCLK Func EMIF_DLL_FC LK EMIF_DLL_GCLK EMIF_DLL_GCLK DPLL_DDR DLL_AGING FCLK Int 38.4 L3INSTR_DLL_AGING _GCLK SYS_CLK1 OSC1 DPLL_ABE_X2_CL K DPLL_ABE DMA_CRYPTO DMA_CRYPTO_FC LK Int & Func 266 L4SEC_L3_GICLK CORE_X2_CLK DPLL_CORE DMA_CRYPTO_IC LK Int 133 L4SEC_L4_GICLK CORE_X2_CLK DPLL_CORE DMM DMM_CLK Int 266 EMIF_L3_GICLK CORE_X2_CLK DPLL_CORE DPLL_DEBUG SYSCLK Int 38.4 EMU_SYS_CLK SYS_CLK1 OSC1 DSP1 DSP1_FICLK Int & Func DSP_CLK DSP1_GFCLK DSP_GFCLK DPLL_DSP DSP2 DSP2_FICLK Int & Func DSP_CLK DSP2_GFCLK DSP_GFCLK DPLL_DSP |
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