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DRA752ABC Datasheet(PDF) 175 Page - Texas Instruments |
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DRA752ABC Datasheet(HTML) 175 Page - Texas Instruments |
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175 / 443 page  175 DRA756, DRA755, DRA754, DRA752 DRA751, DRA750, DRA746, DRA745, DRA744 www.ti.com SPRS950F – DECEMBER 2015 – REVISED MAY 2019 Submit Documentation Feedback Product Folder Links: DRA756 DRA755 DRA754 DRA752 DRA751 DRA750 DRA746 DRA745 DRA744 Specifications Copyright © 2015–2019, Texas Instruments Incorporated NOTE USB1 and USB2 Electrical Characteristics are compliant with USB2.0 Specification Rev 2.0 dated April 27, 2000 including ECNs and Errata as applicable. 5.7.11 Dual Voltage SDIO1833 DC Electrical Characteristics Table 5-18 summarizes the DC electrical characteristics for Dual Voltage SDIO1833 Buffers. Table 5-18. Dual Voltage SDIO1833 DC Electrical Characteristics PARAMETER MIN NOM MAX UNIT Signal Names in Mode 0: mmc1_clk, mmc1_cmd, mmc1_data[3:0] Bottom Balls: W6 / Y6 / AA6 / Y4 / AA5 / Y3 1.8-V Mode VIH Input high-level threshold 1.27 V VIL Input low-level threshold 0.58 V VHYS Input hysteresis voltage 50(2) mV IIN Input current at each I/O pin 30 µA IOZ IOZ(IPAD Current) for BIDI cell. This current is contributed by the tristated driver leakage + input current of the Rx + weak pullup/pulldown leakage. PAD is swept from 0 to VDDS and the Max(I(PAD)) is measured and is reported as IOZ 30 µA IIN with pulldown enabled Input current at each I/O pin with weak pulldown enabled measured when PAD = VDDS 50 120 210 µA IIN with pullup enabled Input current at each I/O pin with weak pullup enabled measured when PAD = 0 60 120 200 µA CPAD Pad capacitance (including package capacitance) 5 pF VOH Output high-level threshold (IOH = 2 mA) 1.4 V VOL Output low-level threshold (IOL = 2 mA) 0.45 V 3.3-V Mode VIH Input high-level threshold 0.625 × VDDS V VIL Input low-level threshold 0.25 × VDDS V VHYS Input hysteresis voltage 40(2) mV IIN Input current at each I/O pin 110 µA IOZ IOZ(IPAD Current) for BIDI cell. This current is contributed by the tristated driver leakage + input current of the Rx + weak pullup/pulldown leakage. PAD is swept from 0 to VDDS and the Max(I(PAD)) is measured and is reported as IOZ 110 µA IIN with pulldown enabled Input current at each I/O pin with weak pulldown enabled measured when PAD = VDDS 40 100 290 µA IIN with pullup enabled Input current at each I/O pin with weak pullup enabled measured when PAD = 0 10 100 290 µA CPAD Pad capacitance (including package capacitance) 5 pF VOH Output high-level threshold (IOH = 2 mA) 0.75 × VDDS V VOL Output low-level threshold (IOL = 2 mA) 0.125 × VDDS V |
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