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TMS320DM641 Datasheet(PDF) 47 Page - Texas Instruments |
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TMS320DM641 Datasheet(HTML) 47 Page - Texas Instruments |
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47 / 179 page  Pin Assignments 47 June 2003 − Revised October 2005 SPRS222E Table 1−6. Terminal Functions (Continued) SIGNAL DESCRIPTION IPD/ IPU‡ TYPE† NAME DESCRIPTION IPD/ IPU‡ TYPE† DM640 DM641 EMIFA (32-BIT) − ADDRESS AEA22 U23 U23 EMIFA t l dd (d bl d dd ) AEA21 V24 V24 EMIFA external address (doubleword address) EMIFA address numbering for the DM641/DM640 devices start with AEA3 to AEA20 V25 V25 EMIFA address numbering for the DM641/DM640 devices start with AEA3 to maintain signal name compatibility with other C64x™ devices (e.g., C6414, AEA19 V26 V26 maintain signal name compatibility with other C64x devices (e.g., C6414, C6415, and C6416) [see the 32-bit EMIF addressing scheme in the TMS320C6000 DSP E t l M I t f (EMIF) R f G id AEA18 V23 V23 TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (literature number SPRU266)] AEA17 U24 U24 (literature number SPRU266)]. AEA16 U25 U25 Boot Configuration: Controls initialization of DSP modes at reset (I) via pullup/pulldown AEA15 U26 U26 • Controls initialization of DSP modes at reset (I) via pullup/pulldown resistors AEA14 T24 T24 resistors − Boot mode (AEA[22:21]): AEA13 T25 T25 O/Z IPD Boot mode (AEA[22:21]): 00 – No boot (default mode) 01 HPI [DM641 only]; Reserved [For DM640 device] AEA12 R23 R23 O/Z IPD 01 − HPI [DM641 only]; Reserved [For DM640 device] 10 − Reserved AEA11 R24 R24 10 − Reserved 11 − EMIFA 8−bit ROM boot AEA10 P23 P23 8 b O boo EMIF clock select AEA9 P24 P24 − EMIF clock select AEA8 P26 P26 − AEA[20:19]: Clock mode select for EMIFA (AECLKIN_SEL[1:0]) AEA7 N23 N23 [] ( _ []) 00 – AECLKIN (default mode) 01 CPU/4 Clock Rate AEA6 N24 N24 01 − CPU/4 Clock Rate 10 − CPU/6 Clock Rate AEA5 N26 N26 10 − CPU/6 Clock Rate 11 − Reserved AEA4 M23 M23 For more details see the Device Configurations section of this data sheet AEA3 M24 M24 For more details, see the Device Configurations section of this data sheet. EMIFA (32-BIT) − DATA AED31 C26 C26 AED30 C25 C25 AED29 D26 D26 AED28 D25 D25 AED27 E24 E24 AED26 E25 E25 AED25 F24 F24 AED24 F25 F25 AED23 F23 F23 I/O/Z IPU EMIFA external data AED22 F26 F26 I/O/Z IPU EMIFA external data AED21 G24 G24 AED20 G25 G25 AED19 G23 G23 AED18 G26 G26 AED17 H23 H23 AED16 H24 H24 AED15 C19 C19 AED14 D19 D19 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) § These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. |
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