TMS320DM641 datasheet(90/179 Pages) TI

90 / 179 page

Enhanced Direct Memory Access (EDMA) Controller

June 2003 − Revised October 2005

SPRS222E

Table 4−2. Characteristics of the Power-Down Modes

PRWD FIELD

(BITS 15−10)

POWER-DOWN

MODE

WAKE-UP METHOD

EFFECT ON CHIP’S OPERATION

000000

No power-down

—

001001

PD1

Wake by an enabled interrupt

CPU halted (except for the interrupt logic)

Power-down mode blocks the internal clock inputs at the

010001

PD1

Wake by an enabled or

non-enabled interrupt

Power down mode blocks the internal clock inputs at the

boundary of the CPU, preventing most of the CPU’s logic from

switching. During PD1, EDMA transactions can proceed between

peripherals and internal memory.

011010

PD2†

Wake by a device reset

Output clock from PLL is halted, stopping the internal clock

structure from switching and resulting in the entire chip being

halted. All register and internal RAM contents are preserved. All

functional I/O “freeze” in the last state when the PLL clock is

turned off.

011100

PD3†

Wake by a device reset

Input clock to the PLL stops generating clocks. All register and

internal RAM contents are preserved. All functional I/O “freeze” in

the last state when the PLL clock is turned off. Following reset, the

PLL needs time to re-lock, just as it does following power-up.

Wake-up from PD3 takes longer than wake-up from PD2 because

the PLL needs to be re-locked, just as it does following power-up.

All others

Reserved

—

† When entering PD2 and PD3, all functional I/O remains in the previous state. However, for peripherals which are asynchronous in nature or

peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these conditions,

peripherals will not operate according to specifications.

4.3.7

C64x Power-Down Mode with an Emulator

If user power-down modes are programmed, and an emulator is attached, the modes will be masked to allow

the emulator access to the system. This condition prevails until the emulator is reset or the cable is removed

from the header. If power measurements are to be performed when in a power-down mode, the emulator cable

should be removed.

When the DSP is in power-down mode PD2 or PD3, emulation logic will force any emulation execution

command (such as Step or Run) to spin in IDLE. For this reason, PC writes (such as loading code) will fail.

A DSP reset will be required to get the DSP out of PD2/PD3.

4.4

Enhanced Direct Memory Access (EDMA) Controller

The EDMA controller handles all data transfers between the level-two (L2) cache/memory controller and the

device peripherals on the DM641/DM640 DSP. These data transfers include cache servicing, non-cacheable

memory accesses, user-programmed data transfers, and host accesses.

4.4.1

EDMA Device-Specific Information

4.4.1.1

EDMA Channel Synchronization Events

The C64x EDMA supports up to 64 EDMA channels which service peripheral devices and external memory.

Table 4−3 lists the source of C64x EDMA synchronization events associated with each of the programmable

EDMA channels. For the DM641/DM640 device, the association of an event to a channel is fixed; each of the

EDMA channels has one specific event associated with it. These specific events are captured in the EDMA

event registers (ERL, ERH) even if the events are disabled by the EDMA event enable registers (EERL,

EERH). The priority of each event can be specified independently in the transfer parameters stored in the

EDMA parameter RAM. For more detailed information on the EDMA module and how EDMA events are

enabled, captured, processed, linked, chained, and cleared, etc., see the TMS320C6000 DSP Enhanced

Direct Memory Access (EDMA) Controller Reference Guide (literature number SPRU234).

TMS320DM641 Datasheet(PDF) 90 Page - Texas Instruments

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