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TMS320DM641 Datasheet(PDF) 51 Page - Texas Instruments |
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TMS320DM641 Datasheet(HTML) 51 Page - Texas Instruments |
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51 / 179 page  Pin Assignments 51 June 2003 − Revised October 2005 SPRS222E Table 1−6. Terminal Functions (Continued) SIGNAL DESCRIPTION IPD/ IPU‡ TYPE† NAME DESCRIPTION IPD/ IPU‡ TYPE† DM640 DM641 ETHERNET MAC (EMAC) MRCLK G1 G1 I EMAC Media Independent I/F (MII) data, clocks, and control pins for MCRS H3 H3 I p/ ( ) , , p Transmit/Receive. MII transmit clock (MTCLK), MRXER G2 G2 I MII transmit clock (MTCLK), Transmit clock source from the attached PHY. MII transmit data (MTXD[3:0]) MRXDV J4 J4 I MII transmit data (MTXD[3:0]), Transmit data nibble synchronous with transmit clock (MTCLK). MII t a s it e able (MTXEN) MRXD3 H2 H2 I MII transmit enable (MTXEN), This signal indicates a valid transmit data on the transmit data pins MRXD2 J3 J3 I This signal indicates a valid transmit data on the transmit data pins (MTDX[3:0]). MII collision sense (MCOL) MRXD1 J1 J1 I MII collision sense (MCOL) Assertion of this signal during half-duplex operation indicates network collision MRXD0 K4 K4 I collision. During full-duplex operation, transmission of new frames will not begin if thi i i td MTCLK L4 L4 I gg this pin is asserted. MII carrier sense (MCRS) MCOL K2 K2 I MII carrier sense (MCRS) Indicates a frame carrier signal is being received. MII receive data (MRXD[3:0]), MTXEN L3 L3 O/Z MII receive data (MRXD[3:0]), Receive data nibble synchronous with receive clock (MRCLK). MII receive clock (MRCLK) MTXD3 L2 L2 O/Z MII receive clock (MRCLK), Receive clock source from the attached PHY. MII i d lid (MRXDV) MTXD2 M4 M4 O/Z MII receive data valid (MRXDV), This signal indicates a valid data nibble on the receive data pins MTXD1 M2 M2 O/Z This signal indicates a valid data nibble on the receive data pins (MRDX[3:0]). MII receive error (MRXER), MTXD0 M3 M3 O/Z MII receive error (MRXER), Indicates reception of a coding error on the receive data. MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0) CONTROL AHCLKX0 AC12 AC12 I/O/Z IPD McASP0 transmit high-frequency master clock (I/O/Z). AFSX0 AD12 AD12 I/O/Z IPD McASP0 transmit frame sync or left/right clock (LRCLK) (I/O/Z). ACLKX0 AB13 AB13 I/O/Z IPD McASP0 transmit bit clock (I/O/Z). AMUTE0 AC13 AC13 O/Z IPD McASP0 mute output (O/Z). AMUTEIN0 AD13 AD13 I/O/Z IPD McASP0 mute input (I/O/Z). AHCLKR0 AB14 AB14 I/O/Z IPD McASP0 receive high-frequency master clock (I/O/Z). AFSR0 AC14 AC14 I/O/Z IPD McASP0 receive frame sync or left/right clock (LRCLK) (I/O/Z). ACLKR0 AD14 AD14 I/O/Z IPD McASP0 receive bit clock (I/O/Z). MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0) DATA AXR0[3] AE11 AE11 AXR0[2] AC10 AC10 I/O/Z IPD McASP0 TX/RX data pins [3:0] (I/O/Z) AXR0[1] AD10 AD10 I/O/Z IPD McASP0 TX/RX data pins [3:0] (I/O/Z). AXR0[0] AC9 AC9 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) § These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. |
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