 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
TMS320DM641 Datasheet(PDF) 114 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
TMS320DM641 Datasheet(HTML) 114 Page - Texas Instruments |
|
|
114 / 179 page  External Memory Interface (EMIIF) 114 June 2003 − Revised October 2005 SPRS222E AECLKOUTx ACEx ABE[3:0] AEA[12:3] AED[31:0] AEA13 AAOE/ASDRAS/ASOE† AARE/ASDCAS/ASADS/ ASRE† AAWE/ASDWE/ASWE† AEA[22:14] BE1 BE2 BE3 BE4 Bank Column D1 D2 D3 D4 8 7 6 5 5 5 1 3 2 8 4 4 4 1 READ APDT‡ 14 14 † AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS, respectively, during SDRAM accesses. ‡ APDT signal is only asserted when the EDMA is in PDT mode (set the PDTS bit to 1 in the EDMA options parameter RAM). For APDT read, data is not latched into EMIF. The PDTRL field in the PDT control register (PDTCTL) configures the latency of the APDT signal with respect to the data phase of a read transaction. The latency of the APDT signal for a read can be programmed to 0, 1, 2, or 3 by setting PDTRL to 00, 01, 10, or 11, respectively. PDTRL equals 00 (zero latency) in Figure 4−24. Figure 4−24. SDRAM Read Command (CAS Latency 3) for EMIFA |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
