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RH850 Datasheet(PDF) 69 Page - Renesas Technology Corp

Part # RH850
Description  Renesas microcontroller
PDF  182 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

RH850 Datasheet(HTML) 69 Page - Renesas Technology Corp

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Page 69 of 182
R01DS0494ED0100 Rev.1.00
June 16, 2025
RH850/U2A
Section 3 Electrical Characteristics
Note 1.
To reach internal usable clocks only following 4 frequencies are supported: 16MHz, 20MHz, 24MHz and
40MHz. Tolerance of external quartz crystal is assumed as +/–1%.
Note 2.
The StartUp is supported without external components under following conditions:
• See RH850/U2A-EVA Group User's Manual: Hardware
Section 51.12.16, OPBT10 — Option Byte 10
for default values of drivability, damping resistance and internal capacitance.
• Specification covers a maximum external stray capacitance of up to 6pF to each pin X1 and X2.
• After StartUp drivability and capacitance will be configured by OPBT10
• A possible exceeding of the recommended maximum drive level for a crystal for all start-up phases has to
be agreed with the crystal manufacturers separately.
Note 3.
Ccapsel_x1 (Ccapsel_x1 including parasitic capacitance to ground at the X1 side), Ccapsel_x2
(Ccapsel_x2 including parasitic capacitance to ground at the X2 side).
Note 4.
The capacitor tolerance is ±15%.
Note 5.
The clock source of SGMII used. Ethernet grade crystal is mandatory. Example: CX3225GA(KYOCERA)
Note 6.
12 kHz to 20 MHz rms jitter = 3 ps.
CAUTION
Oscillation stabilization times differ according to matching with the resonator. Secure
an oscillation stabilization time determined through evaluation of matching.
X1 clock Input high level pulse
width
tEXH
EXCLK mode
fEX = 16 MHz 26
ns
fEX = 20 MHz 20
ns
fEX = 24 MHz 16
ns
fEX = 40 MHz 10
ns
X1 clock rise time
tEXR
EXCLK mode
fEX = 16 MHz
4
ns
fEX = 20 MHz
4
ns
fEX = 24 MHz
3
ns
fEX = 40 MHz
2.5
ns
X1 clock fall time
tEXF
EXCLK mode
fEX = 16 MHz
4
ns
fEX = 20 MHz
4
ns
fEX = 24 MHz
3
ns
fEX = 40 MHz
2.5
ns
X1 clock Input total jitter
(Dj + 14 * rms Random jitter)
tCITJ
The clock source of SGMII used
@ 20MHz
73*6
ps peak
to peak
X1 Input capacitance
CX1
Main OSC. EXCLK mode,
MOSC_CAP_SEL = 0010
10
pF
Table 3.3
Main Oscillator Characteristics (3/3)
Item
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Figure 3.1
Oscillator Circuit Diagram (Crystal with External Components)
X1
X2



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