RH850 datasheet(24/182 Pages) RENESAS

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Page 24 of 182

R01DS0494ED0100 Rev.1.00

June 16, 2025

RH850/U2A

Section 1 Overview

Figure 1.17

Internal Block Diagram (U2A6 156 pins)

System Bus

Debug

ICUM

P-Bus Group1

P-Bus Group2H/2L

P-Bus Group6H/L

IPIR

Global FLASH Bus

CRAM Bus

P-Bus Group4

P-Bus Group7

P-Bus Group8

P-Bus Group0

DMA Controller

sDMAC0,1

WAKE UP

GTM

Data FLASH

INTC2

PSI5S1

RLIN3

(2n, n = 0,

2, 4, 5)

ADCJ0

RSENT0-7

Flash

Controller

Clock

Monitor0-7

Voltage

Monitor

Standby

Controller

SINT

Clock

Controller

Reset

Controller

Temperature

Sensor

IO port

Peripheral Bus(P-Bus)

Inter-cluster Bus(I-Bus)

TPTM

BARR

I-Bus Group2

I-Bus Group1

I-Bus Group0

Local FLASH Bus

LRAM

(64KB)

Icache

CPU0(PE0)

Checker Core

CPU1(PE1)

Checker Core

Cluster #0

LRAM

(64KB)

Icache

Inter-processor element Bus

TAUJ2, 3

RTCA0

P-Bus Group3

KCRC0,2,4,

MSPI 0,2,4

P-Bus Group5

LTSC

TAUD0,1,2

TAPA0,3

TAUJ0,1

TSG31

PIC1

OSTM0-

5,8,9

WDTB0-1

SWDT

MSPI 1,3,5

ADCJ1

RIIC0,1

RS-

CANFD0

TPBA0,1

KCRC1,3,5,

RLIN3

(2n+1, n =1,

2, 4, 5)

PWM-diag

WDTBA

Cluster #3

PIC20,1,2

Code Flash

FLI0

(3MB)

FLI1

(3MB)

Debug

ICUM

P-Bus Group9

High speed Bus(H-Bus)

FlexRay0

H-Bus Group1

RS-

CANFD1

PSI50,1,2,3

DTS

Error Control

Module

MPU

CPU

peripheral

INTC1

FPU

MPU

CPU

peripheral

INTC1

FPU

Cluster0 ERAM

(32KB)

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