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ADSP-21990BBC Datasheet(PDF) 32 Page - Analog Devices |
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ADSP-21990BBC Datasheet(HTML) 32 Page - Analog Devices |
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32 / 50 page ![]() Rev. A | Page 32 of 50 | August 2007 ADSP-21990 External Port Bus Request/Grant Cycle Timing Table 11 and Figure 12 describe external port bus request and bus grant operations. Table 11. External Port Bus Request and Grant Cycle Timing Parameter1, 2 Min Max Unit Timing Requirements tBS BR Asserted to CLKOUT High Setup 4.6 ns tBH CLKOUT High to BR Deasserted Hold Time 0 ns Switching Characteristics tSD CLKOUT High to xMS, Address, and RD/WR Disable 0.5tHCLK + 1 ns tSE CLKOUT Low to xMS, Address, and RD/WR Enable 04ns tDBG CLKOUT High to BG Asserted Setup 0 4 ns tEBG CLKOUT High to BG Deasserted Hold Time 0 4 ns tDBH CLKOUT High to BGH Asserted Setup 0 4 ns tEBH CLKOUT High to BGH Deasserted Hold Time 0 4 ns 1 tHCLK is the peripheral clock period. 2 These are timing parameters that are based on worst-case operating conditions. Figure 12. External Port Bus Request and Grant Cycle Timing tBH A21–0 CLKOUT tBS tSD tSD tSD tDBG tDBH tSE tSE tSE tEBG tEBH BGH WR RD MS3–0 IOMS BMS BR BG |
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