EM78P342NP datasheet(71/102 Pages) EMC

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EM78P341N/342N/343N

8-Bit Microprocessor with OTP ROM

Product Specification (V1.0) 12.01.2006

• 65

(This specification is subject to change without further notice)

TCCBH / MSB Counter (IOC71):

IOC71 is an 8-bit clock counter for the most significant byte of TCCBX

(TCCBH). It can be read, written to, and cleared on any reset condition.

When TCCBHE (IOC90) is “0,” then TCCBH is disabled. When TCCBHE is”1,”

then TCCB is a 16-bit length counter.

NOTE

When TCCBH is Disabled:

TCCB timeout period [1/Fosc x ( 256 - TCCB cnt ) x 1 (CLK=2)]

TCCB timeout period [1/Fosc x ( 256 - TCCB cnt ) x 2 (CLK=4)]

When TCCBH is Enabled:

TCCB timeout period {1/Fosc x [ 65536 - (TCCBH * 256 + TCCB cnt)] x 1 (CLK=2)}

TCCB timeout period {1/Fosc x [ 65536 - (TCCBH * 256 + TCCB cnt)] x 2 (CLK=4)}

TCCC Counter (IOC81):

IOC81 (TCCC) is an 8-bit clock counter. It can be read, written to, and cleared

on any reset condition.

If HF (Bit 2 of IOCA0) = 1 and IRE (Bit 3 of IOCA0) = 1, TCCC counter scale

uses the low-time segments of the pulse generated by Fcarrier frequency

modulation (see Fig. 6-11 in Section 6.8.2, Function Description). The TCCC

value will then be the TCCC predicted value.

When HP = 0 or IRE = 0. The TCCC is an Up Counter.

NOTE

In TCCC Up Counter mode:

■ TCCC timeout period [1/Fosc x scaler (IOCA0) x (256-TCCC cnt) x 1(CLK=2)]

■ TCCC timeout period [1/Fosc x scaler (IOCA0) x (256-TCCC cnt) x 2(CLK=4)]

When HP = 1 and IRE = 1, the TCCC counter scale uses the low-time

segments of the pulse generated by the Fcarrier frequency modulation.

NOTE

In IR mode:

■ Fcarrier = FT/ 2 { [1+decimal TCCC Counter value (IOC81)] x TCCC Scale (IOCA0) }

■ FT is system clock: FT = Fosc/1 (CLK=2)

FT = Fosc/2 (CLK=4)

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