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ADUCM320BBCZ Datasheet(PDF) 6 Page - Analog Devices |
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ADUCM320BBCZ Datasheet(HTML) 6 Page - Analog Devices |
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6 / 31 page ![]() Data Sheet ADuCM320 Rev. C | Page 5 of 30 SPECIFICATIONS MICROCONTROLLER ELECTRICAL SPECIFICATIONS AVDD = IOVDD = VDD1 = 2.9 V to 3.6 V (see Figure 14) maximum difference between supplies = 0.3 V, VREF = 2.5 V internal reference, fCORE = 80 MHz, TA = −40°C to +85°C, unless otherwise noted. PVDDx for IDACs = 1.8 V to 2.5 V. Power-up sequence must be VDD1, IOVDDx, AVDDx, and then PVDDx, but no delays in the sequence are required. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments ADC BASIC SPECIFICATIONS Single-ended mode, unless otherwise stated ADC Power-Up Time 5 µs Data Rate fSAMPLE 1 MSPS DC Accuracy1 14 Bits 1 LSB = 2.5 V/214 Resolution1 16 Bits Number of data bits Integral Nonlinearity INL ±1.75 LSB 2.5 V internal reference; 1 LSB = 2.5 V/214 ±1.75 LSB 2.5 V external reference; 1 LSB = 2.5 V/214 Differential Nonlinearity DNL −0.99 ±0.75 +1 LSB 2.5 V internal reference; 1 LSB = 2.5 V/214 ±0.75 LSB 2.5 V external reference; 1 LSB = 2.5 V/214 DC Code Distribution ±3 LSB ADC input 1.25 V; 1 LSB = 2.5 V/214 ADC ENDPOINT ERRORS Offset Error Input Buffer Off ±200 µV Drift1 −2.25 +1.2 µV/°C Using 2.5 V external reference Input Buffer On −250 µV Drift1 −2.6 +2 µV/°C Using 2.5 V external reference Match ±1 LSB Matching compared to AIN8 Full-Scale Error Input Buffer Off ±400 µV Gain Drift1 −4 +2 µV/°C Full-scale error drift minus offset error drift Input Buffer On −350 µV Gain Drift1 −4.5 +3 µV/°C Full-scale error drift minus offset error drift Match ±1 LSB ADC DYNAMIC PERFORMANCE fIN = 665.25 Hz sine wave, fSAMPLE = 100 kSPS; input filter = 15 Ω, 2 nF Signal-to-Noise Ratio SNR Includes distortion and noise components Input Buffer Disabled 80 dB Enabled 74 dB Total Harmonic Distortion THD Input Buffer Disabled −86 dB Enabled −83 dB Peak Harmonic or Spurious Noise −88 dB Channel-to-Channel Crosstalk −90 dB Measured on adjacent channels ADC INPUT Input buffer not enabled Input Voltage Ranges Single-Ended Mode1 AGND4 VREF Differential Mode1 −VREF +VREF V Voltage between differential pins Compliance1 AGND4 AVDD4 Common Mode1 0.9 1.6 V |
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