ADUCM320BBCZ datasheet(23/31 Pages) AD

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ADuCM320

Data Sheet

Rev. C | Page 22 of 30

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 8. Pin Configuration

Table 11. Pin Function Descriptions

No.

Mnemonic

Type1

Description

RESET

Reset Input (Active Low). An internal pull-up resistor is included.

P0.0/SCLK0/PLAI[0]

I/O

Digital I/O Port 0.0 (P0.0).

SPI0 Clock (SCLK0).

Input to PLA Element 0 (PLAI[0]).

P0.1/MISO0/PLAI[1]

I/O

Digital I/O Port 0.1 (P0.1).

SPI0 Master In, Slave Out (MISO0).

Input to PLA Element 1 (PLAI[1]).

P0.2/MOSI0/PLAI[2]

I/O

Digital I/O Port 0.2 (P0.2).

SPI0 Master Out, Slave In (MOSI0).

Input to PLA Element 2 (PLAI[2]).

P0.3/IRQ0/CS0/PLACLK0/PLAI[3]

I/O

Digital I/O Port 0.3 (P0.3).

External Interrupt 0 (IRQ0).

SPI0 Chip Select 0 (CS0). When using SPI0, configure this pin as CS0.

PLA Clock 0 (PLACLK0).

Input to PLA Element 3 (PLAI[3]).

P0.4/SCL0/PLAO[2]

I/O

Digital I/O Port 0.4 (P0.4).

I2C0 Serial Clock (SCL0).

Output of PLA Element 2 (PLAO[2]).

P0.5/SDA0/PLAO[3]

I/O

Digital I/O Port 0.5 (P0.5).

I2C0 Serial Data (SDA0).

Output of PLA Element 3 (PLAO[3]).

IDAC_

TST

IDAC0

IDAC2

IOVDD1

IOGND1

P3.3/

PRTADDR3/

PLAI[15]

P0.0/

SCLK0/

PLAI[0]

CDAMP0

CDAMP2

CDAMP3

CDAMP1

IDAC1

IREF

IDAC3

PGND

DGND2

SWCLK

AIN15/

P4.7

AIN14/

P4.6

AIN12/

P4.4

AIN11/

BUF_

VREF2V5

AIN10

AIN7

AIN2

AIN1

AIN0

AGND1

VDAC4

VDAC7/

P5.2

VDAC6/

P5.1

XTALI

IOVDD3

IOGND3

VDAC3/

P5.0

VDAC1

VDD1

AVDD3

AGND2

AGND3

AIN3

AIN4

AIN6

AIN5

AIN9/

P4.3

AIN8/

P4.2

VDAC0/

P5.3

VDAC2/

P3.7/

PLAO[29]

VDAC5

DGND1

AGND4

AIN13/

P4.5

AVDD4

SWDIO

IOGND2

IOVDD2

PGND

PVDD0

PVDD2

PVDD3

PVDD1

RESET

P1.0/SIN/

ECLKIN/

PLAI[4]

P1.2/

PWM0/

PLAI[6]

P1.1/SOUT/

PLACLK1/

PLAI[5]

P2.4/IRQ5/

ADCCONV/

PWM6/

PLAO[18]

P1.3/

PWM1/

PLAI[7]

P1.4/

PWM2/

SCLK1/

PLAO[10]

P1.5/

PWM3/

MISO1/

PLAO[11]

P1.6/

PWM4/

MOSI1/

PLAO[12]

P1.7/IRQ1/

PWM5/

CS1/

PLAO[13]

P2.0/IRQ2/

PWMTRIP/

PLACLK2/

PLAI[8]

P2.2/

IRQ4/POR/

CLKOUT/

PLAI[10]

P2.3/BM

P0.2/

MOSI0/

PLAI[2]

P0.5/

SDA0/

PLAO[3]

P2.6/

IRQ7/

PLAO[20]

P0.7/

SDA1/

PLAO[5]

P0.6/

SCL1/

PLAO[4]

P3.0/

PRTADDR0/

PLAI[12]

P3.1/

PRTADDR1/

PLAI[13]

P2.7/

IRQ8/

PLAO[21]

P3.5/

MCK/

PLAO[27]

XTALO

MDIO

P0.4/

SCL0/

PLAO[2]

P0.3/

IRQ0/CS0/

PLACLK0/

PLAI[3]

P0.1/

MISO0/

PLAI[1]

P3.2/

PRTADDR2/

PLAI[14]

P3.4/

PRTADDR4/

PLAO[26]

AVDD_

REG0

AVDD_

REG1

VREF_1V2

ADC_

REFP

ADC_

REFN

DVDD_

2V5

DVDD_1V8

ADuCM320

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