AD7152/AD7153

Rev. 0 | Page 2 of 24

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagrams............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Specifications .................................................................. 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Typical Performance Characteristics ............................................. 8

Serial Interface ................................................................................ 11

Write Operation.......................................................................... 11

Read Operation........................................................................... 11

AD7152/AD7153 Reset ............................................................. 12

General Call................................................................................. 12

Register Map.................................................................................... 13

Status Register ............................................................................. 14

Data Registers ............................................................................. 15

Offset Calibration Registers ...................................................... 15

Gain Calibration Registers ........................................................ 15

CAP Setup Registers .................................................................. 16

Configuration Register .............................................................. 16

CAPDAC POS Register ............................................................. 17

CAPDAC NEG Register ............................................................ 17

Configuration2 Register ............................................................ 17

Circuit Description......................................................................... 18

Capacitance-to-Digital Converter (CDC) .............................. 18

Excitation Source........................................................................ 18

CAPDAC ..................................................................................... 19

Single-Ended Capacitive Input................................................. 19

Differential Capacitive Input .................................................... 20

Parasitic Capacitance to Ground.............................................. 20

Parasitic Resistance to Ground................................................. 20

Parasitic Parallel Resistance ...................................................... 21

Parasitic Serial Resistance ......................................................... 21

Input EMC Protection ............................................................... 21

Power Supply Decoupling and Filtering.................................. 21

Capacitive Gain Calibration ..................................................... 21

Capacitive System Offset Calibration...................................... 21

Typical Application Diagram.................................................... 22

Outline Dimensions ....................................................................... 23

Ordering Guide .......................................................................... 23

REVISION HISTORY

5/08—Revision 0: Initial Version