 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AD8158 Datasheet(PDF) 4 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD8158 Datasheet(HTML) 4 Page - Analog Devices |
|
|
4 / 36 page  AD8158 Rev. 0 | Page 4 of 36 Parameter Conditions Min Typ Max Unit Supply Current DC-coupled inputs/outputs, 400 mV I/O swings (800 mV p-p differential), 50 Ω far-end terminations ICC 354 450 mA ITTO 128 150 mA ITTI 94 107 mA IDVCC 2 4 mA Supply Current LB_x = 1, PE = 6 dB on all ports, dc-coupled inputs/outputs, 400 mV I/O swings (800 mV p-p differential), 50 Ω far-end terminations ICC 730 850 mA ITTO 367 420 mA ITTI 95 107 mA IDVCC 2 4 mA THERMAL CHARACTERISTICS Operating Temperature Range −40 +85 °C θJA Still air; JEDEC four-layer test board, ePAD soldered 22.2 °C/W θJC Still air; thermal resistance through exposed pad 1.4 °C/W Maximum Junction Temperature 125 °C LOGIC INPUT CHARACTERISTICS3 I2C, SDA, SCL, control pins Input High (VIH) DVCC = 3.3 V 0.7 × DVCC DVCC V Input Low (VIL) DVCC = 3.3 V VEE 0.3 × DVCC V Input High (VIH) DVCC = 1.8 V 0.8 × DVCC DVCC V Input Low (VIL) DVCC = 1.8 V VEE 0.2 × DVCC V 1 Bicast is off, loopback is off on all ports, pre-emphasis is set to minimum on all ports, and equalization is set to minimum on all ports. 2 VICM is the input common-mode voltage. 3 EQ control pins (EQ_A0, EQ_A1, EQ_B0, EQ_B1, EQ_C0, EQ_C1) require 5 kΩ in series when DVCC > VCC. I2C TIMING SPECIFICATIONS SCL S Sr S P SDA tF tLOW tHD;STA tHD;DAT tSU;DAT tSU;STA tHD;STA tHIGH tR tF tSU;STO tR tBUF Figure 2. I2C Timing Diagram Table 2. I2C Timing Parameters Parameter Symbol Min Max Unit SCL Clock Frequency fSCL 0 400+ kHz Hold Time for a Start Condition tHD;STA 0.6 μs Setup Time for a Repeated Start Condition tSU;STA 0.6 μs Low Period of the SCL Clock tLOW 1.3 μs High Period of the SCL Clock tHIGH 0.6 μs Data Hold Time tHD;DAT 0 μs Data Setup Time tSU;DAT 10 ns Rise Time for Both SDA and SCL tR 1 300 ns Fall Time for Both SDA and SCL tF 1 300 ns Setup Time for Stop Condition tSU;STO 0.6 μs Bus Free Time Between a Stop and a Start Condition tBUF 1 ns Capacitance for Each I/O Pin Ci 5 7 pF |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
